DS92CK16

ACTIVE

3-V BLVDS 1 to 6 clock buffer/bus transceiver

Product details

Function Buffer, Transceiver Protocols BLVDS, CMOS Number of transmitters 6 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 250 Input signal BLVDS Output signal CMOS Rating Catalog Operating temperature range (°C) -40 to 85
Function Buffer, Transceiver Protocols BLVDS, CMOS Number of transmitters 6 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 250 Input signal BLVDS Output signal CMOS Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (PW) 24 49.92 mm² 7.8 x 6.4
  • Master/Slave Clock Selection in a Backplane Application
  • 125 MHz Operation (Typical)
  • 100 ps Duty Cycle Distortion (Typical)
  • 50 ps Channel to Channel Skew (Typical)
  • 3.3V Power Supply Design
  • Glitch-free Power on at CLKI/O Pins
  • Low Power Design (20 mA @ 3.3V Static)
  • Accepts Small Swing (300 mV Typical) Differential Signal Levels
  • Industrial Temperature Operating Range (-40°C to +85°C)
  • Available in 24-pin TSSOP Packaging

All trademarks are the property of their respective owners.

  • Master/Slave Clock Selection in a Backplane Application
  • 125 MHz Operation (Typical)
  • 100 ps Duty Cycle Distortion (Typical)
  • 50 ps Channel to Channel Skew (Typical)
  • 3.3V Power Supply Design
  • Glitch-free Power on at CLKI/O Pins
  • Low Power Design (20 mA @ 3.3V Static)
  • Accepts Small Swing (300 mV Typical) Differential Signal Levels
  • Industrial Temperature Operating Range (-40°C to +85°C)
  • Available in 24-pin TSSOP Packaging

All trademarks are the property of their respective owners.

The DS92CK16 1 to 6 Clock Buffer/Bus Transceiver is a one to six CMOS differential clock distribution device utilizing Bus Low Voltage Differential Signaling (BLVDS) technology. This clock distribution device is designed for applications requiring ultra low power dissipation, low noise, and high data rates. The BLVDS side is a transceiver with a separate channel acting as a return/source clock.

The DS92CK16 accepts LVDS (300 mV typical) differential input levels, and translates them to 3V CMOS output levels. An output enable pin OE , when high, forces all CLKOUT pins high.

The device can be used as a source synchronous driver. The selection of the source driving is controlled by the CrdCLKIN and DE pins. This device can be the master clock, driving the inputs of other clock I/O pins in a multipoint environment. Easy master/slave clock selection is achieved along a backplane.

The DS92CK16 1 to 6 Clock Buffer/Bus Transceiver is a one to six CMOS differential clock distribution device utilizing Bus Low Voltage Differential Signaling (BLVDS) technology. This clock distribution device is designed for applications requiring ultra low power dissipation, low noise, and high data rates. The BLVDS side is a transceiver with a separate channel acting as a return/source clock.

The DS92CK16 accepts LVDS (300 mV typical) differential input levels, and translates them to 3V CMOS output levels. An output enable pin OE , when high, forces all CLKOUT pins high.

The device can be used as a source synchronous driver. The selection of the source driving is controlled by the CrdCLKIN and DE pins. This device can be the master clock, driving the inputs of other clock I/O pins in a multipoint environment. Easy master/slave clock selection is achieved along a backplane.

Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 2
Type Title Date
* Data sheet DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver datasheet (Rev. C) 13 Apr 2013
Application note High Speed BUS LVDS Clock Distri Using DS92CK16 Clock Distri (Rev. B) 26 Apr 2013

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation model

DS92CK16 IBIS Model

SNAM029.ZIP (6 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
Package Pins CAD symbols, footprints & 3D models
TSSOP (PW) 24 Ultra Librarian

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos