The DSLVDS1048 device is a quad CMOS flow-through differential line receiver designed for applications requiring ultra-low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) using Low Voltage Differential Signaling (LVDS) technology.
The DSLVDS1048 accepts low voltage (350 mV typical) differential input signals and translates them to 3-V CMOS output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports open, shorted, and terminated (100-Ω) input fail-safe. The receiver output is HIGH for all fail-safe conditions. The DSLVDS1048 has a flow-through pinout for easy PCB layout.
The EN and EN* inputs are ANDed together and control the TRI-STATE outputs. The enables are common to all four receivers. The DSLVDS1048 and companion LVDS line driver (for example, DSLVDS1047) provide a new alternative to high-power PECL/ECL devices for high-speed point-to-point interface applications.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | DSLVDS1048 3.3-V LVDS Quad Channel High-Speed Differential Line Receiver datasheet | PDF | HTML | 27 Sep 2018 |
| Application note | Applications of Low-Voltage Differential Signaling (LVDS) in LED Walls | 29 Oct 2020 | ||
| Application note | Applications of Low-Voltage Differential Signaling (LVDS) in Ultrasound Scanners | 29 Jun 2019 | ||
| Application brief | LVDS to Improve EMC in Motor Drives | 27 Sep 2018 | ||
| Application brief | How Far, How Fast Can You Operate LVDS Drivers and Receivers? | 03 Aug 2018 | ||
| Application brief | How to Terminate LVDS Connections with DC and AC Coupling | 16 May 2018 | ||
| Application note | An Overview of LVDS Technology | 05 Oct 1998 |
For additional terms or required resources, click any title below to view the detail page where available.
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| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| TSSOP (PW) | 16 | Ultra Librarian |
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