Packaging information
| Package | Pins SOIC (D) | 8 |
| Operating temperature range (°C) -55 to 125 |
| Package qty | Carrier 2,500 | LARGE T&R |
Features for the ISO721M-EP
- Controlled Baseline
- One Assembly Site
- One Test Site
- One Fabrication Site
- Extended Temperature Performance of –55°C to 125°C
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product-Change Notification
- Qualification Pedigree(1)
- 4000-V(peak) Isolation
- UL 1577, IEC 60747-5-2 (VDE 0884, Rev. 2) IEC 61010-1
- 50-kV/µs Transient Immunity Typical
- Signaling Rate 0 Mbps to 150 Mbps
- Low Propagation Delay
- Low Pulse Skew (Pulse-Width Distortion)
- Low-Power Sleep Mode
- High Electromagnetic Immunity
- Low Input Current Requirement
- Failsafe Output
- Drop-In Replacement for Most Opto and Magnetic Isolators
- APPLICATIONS
- Industrial Fieldbus
- Modbus
- Profibus
- DeviceNet Data Buses
- Smart Distributed Systems (SDS)
- Computer Peripheral Interface
- Servo Control Interface
- Data Acquisition
- Industrial Fieldbus
(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
(2) The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
SDS is a trademark of Honeywell.
DeviceNet is a trademark of Open Devicenet Vendors Association, Inc.
Description for the ISO721M-EP
The ISO721, ISO721M, ISO722, and ISO722M are digital isolators with a logic input and output buffer separated by a silicon oxide (SiO2) insulation barrier. This barrier provides galvanic isolation of up to 4000 V. Used in conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuits from entering the local ground, and interfering with or damaging sensitive circuitry.
A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh pulse is not received for more than 4 µs, the input is assumed to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state.
The symmetry of the dielectric and capacitor within the integrated circuitry provides for close capacitive matching, and allows fast transient voltage changes between the input and output grounds without corrupting the output. The small capacitance and resulting time constant provide for fast operation with signaling rates(2) from 0 Mbps (dc) to 100 Mbps for the ISO721/ISO722, and 0 Mbps to 150 Mbps with the ISO721M/ISO722M.
These devices require two supply voltages of 3.3 V, 5 V, or any combination. All inputs are 5-V tolerant when supplied from a 3.3-V supply and all outputs are 4-mA CMOS.
The ISO721 has TTL input thresholds and a noise-filter at the input that prevents transient pulses of up to 2 ns in duration from being passed to the output of the device.
The ISO721M has CMOS VCC/2 input thresholds, but do not have the noise filter and the additional propagation delay. These features of the ISO721M also provide for reduced jitter operation.
The ISO721M is characterized for operation over the ambient temperature range of –55°C to 125°C.