These four devices are high-frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx16) and fully differential inputs on the SN65LVx17.
The SN65LVx16 provides the user a Gain Control (GC) for controlling the Q output from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to VCC. (When left open, the Q output defaults to 575 mV.) The Q on the SN65LVx17 defaults to 575 mV as well.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCC for use in receiving single-ended PECL input signals. When not used, VBB should be unconnected or open.
All devices are characterized for operation from -40°C to 85°C.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | 2.5-V/3.3-V Oscillator Gain Stage/Buffers datasheet (Rev. B) | 18 Nov 2005 | |
| Application note | TMDS Clock Detection Solution in HDMI Sink Applications | 23 Aug 2017 | ||
| EVM User's guide | Translator/Oscillator Buffer EVM (Rev. A) | 17 Sep 2004 |
For additional terms or required resources, click any title below to view the detail page where available.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| WSON (DRF) | 8 | Ultra Librarian |
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