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SN65LVELT23

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3.3-V dual differential LVPECL buffer to LVTTL translator

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Data sheet

SN65LVELT23

ACTIVE
Data sheet Order now

Product details

Function Receiver, Translator Protocols LVDS, LVPECL Number of transmitters 0 Number of receivers 2 Supply voltage (V) 3.3 Signaling rate (Mbps) 600 Input signal LVDS, LVPECL Output signal LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Receiver, Translator Protocols LVDS, LVPECL Number of transmitters 0 Number of receivers 2 Supply voltage (V) 3.3 Signaling rate (Mbps) 600 Input signal LVDS, LVPECL Output signal LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 8 29.4 mm² 4.9 x 6 VSSOP (DGK) 8 14.7 mm² 3 x 4.9
  • Dual 3.3-V Differential LVPECL/LVDS to LVTTL Buffer Translator
  • 24-mA LVTTL Ouputs
  • Operating Range
    • PECL VCC = 3 V to 3.6 V With GND = 0 V
  • Support for Clock Frequencies to >180 MHz
  • 2-ns Typical Propagation Delay
  • Internal Input Pullup and Pulldown Resistors
  • Built-in Temperature Compensation
  • Drop-In Compatible to MC100LVELT23
  • APPLICATIONS
    • Data and Clock Transmission Over Backplane
    • Signaling Level Conversion for Clock or Data
  • Dual 3.3-V Differential LVPECL/LVDS to LVTTL Buffer Translator
  • 24-mA LVTTL Ouputs
  • Operating Range
    • PECL VCC = 3 V to 3.6 V With GND = 0 V
  • Support for Clock Frequencies to >180 MHz
  • 2-ns Typical Propagation Delay
  • Internal Input Pullup and Pulldown Resistors
  • Built-in Temperature Compensation
  • Drop-In Compatible to MC100LVELT23
  • APPLICATIONS
    • Data and Clock Transmission Over Backplane
    • Signaling Level Conversion for Clock or Data

The SN65LVELT23 is a low-power dual LVPECL/LVDS to LVTTL translator device. The device includes circuitry to maintain inputs at VCC/2 when left open. The SN65LVELT23 is housed in an industry-standard SOIC-8 package and is also available in a TSSOP-8 option.

The SN65LVELT23 is a low-power dual LVPECL/LVDS to LVTTL translator device. The device includes circuitry to maintain inputs at VCC/2 when left open. The SN65LVELT23 is housed in an industry-standard SOIC-8 package and is also available in a TSSOP-8 option.
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Technical documentation

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Type Title Date
* Data sheet 3.3V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator datasheet (Rev. A) 03 Aug 2009
Application note AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) 17 Oct 2007

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SN65LVELT23 IBIS Model

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