EPIC-IIB is a trademark of Texas Instruments Incorporated.
The 'ABT833 8-bit to 9-bit parity transceivers are designed for
communication between data buses. When data is transmitted from the A
bus to the B bus, a parity bit is generated. When data is transmitted
from the B bus to the A bus with its corresponding parity bit, the
open-collector parity-error (
) output indicates whether or not an error in the B data
has occurred. The output-enable (
and 
) inputs can be
used to disable the device so that the buses are effectively
isolated. The 'ABT833 provide true data at their outputs.
A 9-bit parity generator/checker generates a parity-odd (PARITY)
output and monitors the parity of the I/O ports with the flag. is clocked into the register on
the rising edge of the clock (CLK) input. The error flag register is
cleared with a low pulse on the clear (
) input. When both and are low, data is transferred from
the A bus to the B bus and inverted parity is generated. Inverted
parity is a forced error condition that gives the designer more
system diagnostic capability.
To ensure the high-impedance state during power up or power down,
should be tied
to VCC through a pullup resistor; the minimum value of the
resistor is determined by the current-sinking capability of the
driver.
The SN54ABT833 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT833 is characterized for operation from -40°C to 85°C.
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The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| SOIC (DW) | 24 | Ultra Librarian |
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