The device contains two independent D-type positive-edge-triggered flip-flops. All inputs include Schmitt triggers, allowing for slow or noisy input signals. A low level at the preset ( PRE) input sets the output high. A low level at the clear ( CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q, Q) on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the input clock (CLK) signal. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q, Q).
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | SN74HCS74 Schmitt-Trigger Input Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset datasheet (Rev. D) | PDF | HTML | 07 Dec 2021 |
| Application brief | Simplifying Solid-State Relay Designs With Logic | PDF | HTML | 08 Jan 2021 |
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The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,
14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| SOIC (D) | 14 | Ultra Librarian |
| SOT-23-THN (DYY) | 14 | Ultra Librarian |
| TSSOP (PW) | 14 | Ultra Librarian |
| WQFN (BQA) | 14 | Ultra Librarian |
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