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SN74LV393A

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Dual 4-Bit Binary Counters

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Data sheet

SN74LV393A

ACTIVE
Data sheet Order now

Product details

Function Counter Bits (#) 4 Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Function Counter Bits (#) 4 Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
SOIC (D) 14 51.9 mm² 8.65 x 6 SOP (NS) 14 79.56 mm² 10.2 x 7.8 SSOP (DB) 14 48.36 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23.04 mm² 3.6 x 6.4
  • VCC operation of 2 V to 5.5 V
  • Max tpd of 10 ns at 5 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Ioff supports Partial-Power-Down-Mode operation
  • Dual 4-bit binary counters with individual clocks
  • Direct clear for each 4-bit counter
  • Can significantly improve system densities by reducing counter package count by 50 percent
  • Latch-Up performance exceeds 100 mA per JESD 78, Class II
  • VCC operation of 2 V to 5.5 V
  • Max tpd of 10 ns at 5 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Ioff supports Partial-Power-Down-Mode operation
  • Dual 4-bit binary counters with individual clocks
  • Direct clear for each 4-bit counter
  • Can significantly improve system densities by reducing counter package count by 50 percent
  • Latch-Up performance exceeds 100 mA per JESD 78, Class II

The ’LV393A devices contain eight flip-flops and additional gating to implement two individual 4-bit counters in a single package. These devices are designed for 2 V to 5.5 V VCC operation.

The ’LV393A devices contain eight flip-flops and additional gating to implement two individual 4-bit counters in a single package. These devices are designed for 2 V to 5.5 V VCC operation.
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Technical documentation

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* Data sheet SN74LV393A Dual 4-Bit Binary Counters datasheet (Rev. E) PDF | HTML 16 Mar 2023

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Reference designs

TIPD169 — 16-Bit, 1MSPS Multiplexed Data Acquisition Reference Design

This design is for a 16-bit 1MSPS single-ended, multiplexed data acquisition system (DAQ) for dc inputs. The system is composed of a 16-bit successive-approximation-register (SAR) analog-to-digital converter (ADC), SAR ADC driver, reference driver, and multiplexer. The design shows the process to (...)
Design guide: PDF
Schematic: PDF
Package Pins CAD symbols, footprints & 3D models
SOIC (D) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
SSOP (DB) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
TVSOP (DGV) 14 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

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