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SN74LVTH16835

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3.3-V ABT 18-Bit Universal Bus Drivers With 3-State Outputs

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Data sheet

SN74LVTH16835

ACTIVE
Data sheet Order now

Product details

Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Number of channels 18 IOL (max) (mA) 64 IOH (max) (mA) -6 Input type TTL-Compatible CMOS Output type 3-State Features Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Technology family LVT Rating Catalog Operating temperature range (°C) -40 to 85
Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Number of channels 18 IOL (max) (mA) 64 IOH (max) (mA) -6 Input type TTL-Compatible CMOS Output type 3-State Features Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Technology family LVT Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DGG) 56 113.4 mm² 14 x 8.1
  • Members of the Texas Instruments WidebusTM Family
  • State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation
  • Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Support Unregulated Battery Operation Down to 2.7 V
  • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 500 mA Per JESD 17
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Package Options Include Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

    Widebus is a trademark of Texas Instruments Incorporated.
  • Members of the Texas Instruments WidebusTM Family
  • State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation
  • Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Support Unregulated Battery Operation Down to 2.7 V
  • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 500 mA Per JESD 17
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Package Options Include Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

    Widebus is a trademark of Texas Instruments Incorporated.

The 'LVTH16835 devices are 18-bit universal bus drivers designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

Data flow from A to Y is controlled by the output-enable (OE\) input. These devices operate in the transparent mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of the clock. When OE\ is high, the outputs are in the high-impedance state.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

The SN54LVTH16835 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVTH16835 is characterized for operation from -40°C to 85°C.

The 'LVTH16835 devices are 18-bit universal bus drivers designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

Data flow from A to Y is controlled by the output-enable (OE\) input. These devices operate in the transparent mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of the clock. When OE\ is high, the outputs are in the high-impedance state.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

The SN54LVTH16835 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVTH16835 is characterized for operation from -40°C to 85°C.

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Technical documentation

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Type Title Date
* Data sheet 3.3-V ABT 18-Bit Universal Bus Drivers With 3-State Outputs datasheet (Rev. C) 07 Apr 1999
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Application note An Overview of Bus-Hold Circuit and the Applications (Rev. B) 17 Sep 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 May 2002
Selection guide Advanced Bus Interface Logic Selection Guide 09 Jan 2001
Application note LVT-to-LVTH Conversion 08 Dec 1998
Application note LVT Family Characteristics (Rev. A) 01 Mar 1998
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

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Simulation model

SN74LVTH16835 IBIS Model

SCEM171.ZIP (21 KB) - IBIS Model
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TSSOP (DGG) 56 Ultra Librarian
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