TB5R2

ACTIVE

Quad PECL line receiver

Product details

Function Receiver Protocols PECL Number of transmitters 0 Number of receivers 4 Supply voltage (V) 5 Signaling rate (Mbps) 100 Input signal PECL Output signal TTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Receiver Protocols PECL Number of transmitters 0 Number of receivers 4 Supply voltage (V) 5 Signaling rate (Mbps) 100 Input signal PECL Output signal TTL Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 16 59.4 mm² 9.9 x 6 SOIC (DW) 16 106.09 mm² 10.3 x 10.3
  • Functional Replacements for the Agere BRF1A, BRF2A, BRS2A, and BRS2B
  • Pin Equivalent to General Trade 26LS32
  • High Input Impedance Approximately 8 k
  • 4-ns Maximum Propagation Delay
  • TB5R1 Provides 50-mV Hysteresis
  • TB5R2 With -125-mV Threshold Offset for Preferred State Output
  • -1.1-V to 7.1-V Common Mode Range
  • Single 5-V ±10% Supply
  • Slew Rate Limited (1 ns min 80% to 20%)
  • TB5R2 Output Defaults to Logic 1 When Inputs Left Open or Shorted to VCC or GND
  • ESD Protection HBM > 3 kV, CDM > 2 kV
  • Operating Temperature Range: -40°C to 85°C
  • Available in Gull-Wing SOIC (JEDEC MS-013, DW) and SOIC (D) Package
  • APPLICATIONS
    • Digital Data or Clock Transmission Over Balanced Lines

  • Functional Replacements for the Agere BRF1A, BRF2A, BRS2A, and BRS2B
  • Pin Equivalent to General Trade 26LS32
  • High Input Impedance Approximately 8 k
  • 4-ns Maximum Propagation Delay
  • TB5R1 Provides 50-mV Hysteresis
  • TB5R2 With -125-mV Threshold Offset for Preferred State Output
  • -1.1-V to 7.1-V Common Mode Range
  • Single 5-V ±10% Supply
  • Slew Rate Limited (1 ns min 80% to 20%)
  • TB5R2 Output Defaults to Logic 1 When Inputs Left Open or Shorted to VCC or GND
  • ESD Protection HBM > 3 kV, CDM > 2 kV
  • Operating Temperature Range: -40°C to 85°C
  • Available in Gull-Wing SOIC (JEDEC MS-013, DW) and SOIC (D) Package
  • APPLICATIONS
    • Digital Data or Clock Transmission Over Balanced Lines

These quad differential receivers accept digital data over balanced transmission lines. They translate differential input logic levels to TTL output logic levels.

The TB5R1 is a pin- and function-compatible replacement for the Agere systems BRF1A and BRF2A; it includes 3-kV HBM and 2-kV CDM ESD protection.

The TB5R2 is a pin- and function-compatible replacement for the Agere systems BRS2A and BRS2B and incorporates a 125-mV receiver input offset, preferred state output, 3-kV HBM and 2-kV CDM ESD protection. The TB5R2 preferred state feature places the high state when the inputs are open, shorted to ground, or shorted to the power supply.

The power-down loading characteristics of the receiver input circuit are approximately 8 k relative to the power supplies; hence they do not load the transmission line when the circuit is powered down.

The packaging for these differential line receivers include a 16-pin gull wing SOIC (DW) and SOIC (D).

The enable inputs of this device include internal pullup resistors of approximately 40 k that are connected to VCC to ensure a logical high level input if the inputs are open circuited.

These quad differential receivers accept digital data over balanced transmission lines. They translate differential input logic levels to TTL output logic levels.

The TB5R1 is a pin- and function-compatible replacement for the Agere systems BRF1A and BRF2A; it includes 3-kV HBM and 2-kV CDM ESD protection.

The TB5R2 is a pin- and function-compatible replacement for the Agere systems BRS2A and BRS2B and incorporates a 125-mV receiver input offset, preferred state output, 3-kV HBM and 2-kV CDM ESD protection. The TB5R2 preferred state feature places the high state when the inputs are open, shorted to ground, or shorted to the power supply.

The power-down loading characteristics of the receiver input circuit are approximately 8 k relative to the power supplies; hence they do not load the transmission line when the circuit is powered down.

The packaging for these differential line receivers include a 16-pin gull wing SOIC (DW) and SOIC (D).

The enable inputs of this device include internal pullup resistors of approximately 40 k that are connected to VCC to ensure a logical high level input if the inputs are open circuited.

Download

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 1
Type Title Date
* Data sheet TB5R1,TB5R2, Quad Differential PECL Receivers datasheet (Rev. C) 18 Jan 2008

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​