Product details

Configuration 2:1 SPDT Number of channels 2 Power supply voltage - single (V) 3.3 Protocols Analog, I2C, I3C, LVDS, UART Ron (typ) (Ω) 6 CON (typ) (pF) 7.5 ON-state leakage current (max) (µA) 1 Bandwidth (MHz) 900 Operating temperature range (°C) -40 to 85 Features 1.8-V compatible control inputs, Powered-off protection, Supports input voltage beyond supply Input/output continuous current (max) (mA) 64 Rating Catalog Drain supply voltage (max) (V) 4.3 Supply voltage (max) (V) 4.3
Configuration 2:1 SPDT Number of channels 2 Power supply voltage - single (V) 3.3 Protocols Analog, I2C, I3C, LVDS, UART Ron (typ) (Ω) 6 CON (typ) (pF) 7.5 ON-state leakage current (max) (µA) 1 Bandwidth (MHz) 900 Operating temperature range (°C) -40 to 85 Features 1.8-V compatible control inputs, Powered-off protection, Supports input voltage beyond supply Input/output continuous current (max) (mA) 64 Rating Catalog Drain supply voltage (max) (V) 4.3 Supply voltage (max) (V) 4.3
UQFN (RSW) 10 2.52 mm² 1.8 x 1.4 VSSOP (DGS) 10 14.7 mm² 3 x 4.9
  • VCC Operation at 3 V to 4.3 V
  • I/O Pins Can Tolerate up to 5.25 V
  • 1.8-V Compatible Control Logic
  • Supports Powered-off Protection I/O Pins Hi-Z When VCC = 0 V
  • RON = 10 Ω Maximum
  • ΔRON = 0.35 Ω Typical
  • Cio(ON) = 7.5 pF Typical
  • Low Power Consumption (1 uA Maximum)
  • –3-dB Bandwidth = 900 MHz Typical
  • Latch-Up Performance Exceeds
    100 mA Per JESD 78, Class II (1)
  • ESD Performance Tested Per JESD 22
    • 8000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • ESD Performance I/O Port to GND (2)
    • 15000-V Human-Body Model

(1)Except EN and SEL Inputs

(2)High-voltage HBM is performed in addition to the standard HBM testing (A114-B, Class II) and applies to I/O ports tested with respect to GND only.

  • VCC Operation at 3 V to 4.3 V
  • I/O Pins Can Tolerate up to 5.25 V
  • 1.8-V Compatible Control Logic
  • Supports Powered-off Protection I/O Pins Hi-Z When VCC = 0 V
  • RON = 10 Ω Maximum
  • ΔRON = 0.35 Ω Typical
  • Cio(ON) = 7.5 pF Typical
  • Low Power Consumption (1 uA Maximum)
  • –3-dB Bandwidth = 900 MHz Typical
  • Latch-Up Performance Exceeds
    100 mA Per JESD 78, Class II (1)
  • ESD Performance Tested Per JESD 22
    • 8000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • ESD Performance I/O Port to GND (2)
    • 15000-V Human-Body Model

(1)Except EN and SEL Inputs

(2)High-voltage HBM is performed in addition to the standard HBM testing (A114-B, Class II) and applies to I/O ports tested with respect to GND only.

The TMUX154E is a high-bandwidth 2:1 switch specially designed for the switching of high-speed signals in applications with limited I/Os. The wide bandwidth (900 MHz) of this switch allows signals to pass with minimum edge and phase distortion. The switch is bidirectional and offers little or no attenuation of high-speed signals. It is designed for low bit-to-bit skew and high channel-to-channel noise isolation.

The TMUX154E integrates ESD protection cells on all pins, is available in a tiny UQFN package (1.8 mm × 1.4 mm) or a VSSOP package, and is characterized over the free-air temperature range of –40°C to 85°C.

The TMUX154E is a high-bandwidth 2:1 switch specially designed for the switching of high-speed signals in applications with limited I/Os. The wide bandwidth (900 MHz) of this switch allows signals to pass with minimum edge and phase distortion. The switch is bidirectional and offers little or no attenuation of high-speed signals. It is designed for low bit-to-bit skew and high channel-to-channel noise isolation.

The TMUX154E integrates ESD protection cells on all pins, is available in a tiny UQFN package (1.8 mm × 1.4 mm) or a VSSOP package, and is characterized over the free-air temperature range of –40°C to 85°C.

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Technical documentation

Design & development

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Interface adapter

LEADED-ADAPTER1 — Surface mount to DIP header adapter for quick testing of TI's 5, 8, 10, 16 & 24-pin leaded packages

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

User guide: PDF
Not available on TI.com
Interface adapter

LEADLESS-ADAPTER1 — Surface mount to DIP header adapter for testing of TI's 6,8,10,12,14,16, & 20-pin leadless packages

The EVM-LEADLESS1 board allows for quick testing and bread boarding of TI's common leadless packages.  The board has footprints to convert TI's DRC, DTP, DQE, RBW, RGY, RSE, RSV, RSW RTE, RTJ, RUK , RUC, RUG, RUM,RUT and YZP surface mount packages to 100mil DIP headers.
User guide: PDF
Not available on TI.com
Simulation model

TMUX154E TINA-TI Reference Design

SCDM178.TSC (409 KB) - TINA-TI Reference Design
Simulation model

TMUX154E TINA-TI Spice Model

SCDM179.ZIP (5 KB) - TINA-TI Spice Model
Package Pins CAD symbols, footprints & 3D models
UQFN (RSW) 10 Ultra Librarian
VSSOP (DGS) 10 Ultra Librarian

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