CD4086B

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CMOS, erweiterbares zweifaches AND-OR-Invertierungs-Gatter, 4 weit, 2 Eingänge

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Datenblatt

document-pdfAcrobat CD4086B TYPES datasheet (Rev. C) (Englisch)

CD4086B

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Technology family

CD4000

Supply voltage (min) (V)

3

Supply voltage (max) (V)

18

Number of channels

1

Inputs per channel

2

IOL (max) (mA)

6.8

IOH (max) (mA)

-6.8

Input type

Standard CMOS

Output type

Push-Pull

Features

Standard speed (tpd > 50ns)

Data rate (max) (Mbps)

8

Rating

Catalog

Operating temperature range (°C)

-55 to 125

Technology family

CD4000

Supply voltage (min) (V)

3

Supply voltage (max) (V)

18

Number of channels

1

Inputs per channel

2

IOL (max) (mA)

6.8

IOH (max) (mA)

-6.8

Input type

Standard CMOS

Output type

Push-Pull

Features

Standard speed (tpd > 50ns)

Data rate (max) (Mbps)

8

Rating

Catalog

Operating temperature range (°C)

-55 to 125

PDIP (N)

14

181.42 mm² 19.3 x 9.4

SOIC (D)

14

51.9 mm² 8.65 x 6

Medium-speed operation - t_PHL = 90 ns; t_PLH = 140 ns (typ.) at 10 V
INHIBIT and ENABLE inputs
Buffered outputs
100% tested for quiescent current at 20 V
Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Noise margin (over full package temperature range):
    1 V at V_DD = 5 V
    2 V at V_DD = 10 V
    2.5 V at V_DD = 15 V
Standardized, symmetrical output characteristics
5-V, 10-V, and 15-V parametric ratings
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"

Medium-speed operation - t_PHL = 90 ns; t_PLH = 140 ns (typ.) at 10 V
INHIBIT and ENABLE inputs
Buffered outputs
100% tested for quiescent current at 20 V
Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Noise margin (over full package temperature range):
    1 V at V_DD = 5 V
    2 V at V_DD = 10 V
    2.5 V at V_DD = 15 V
Standardized, symmetrical output characteristics
5-V, 10-V, and 15-V parametric ratings
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"

CD4086B contains one 4-wide 2-input AND-OR-INVERT gate with an INHIBIT/(EXP\) input and an ENABLE/EXP input. For a 4-wide A-O-I function INHIBIT/(EXP\) is tied to V_SS and ENABLE/EXP to V_DD. See Fig. 10 and its associated explanation for applications where a capability greater than 4-wide is required.

The CD4086B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4086B contains one 4-wide 2-input AND-OR-INVERT gate with an INHIBIT/(EXP\) input and an ENABLE/EXP input. For a 4-wide A-O-I function INHIBIT/(EXP\) is tied to V_SS and ENABLE/EXP to V_DD. See Fig. 10 and its associated explanation for applications where a capability greater than 4-wide is required.

The CD4086B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

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	Typ	Titel		Datum
*	Data sheet	CD4086B TYPES datasheet (Rev. C)		21 Aug 2003

CD4086B

CMOS, erweiterbares zweifaches AND-OR-Invertierungs-Gatter, 4 weit, 2 Eingänge

CD4086B

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