Startseite Logik- & Spannungsumsetzung Konfigurierbare & programmierbare Logik-ICs Multivibrator (One-Shot)
Startseite
Logik- & Spannungsumsetzung
Konfigurierbare & programmierbare Logik-ICs
Multivibrator (One-Shot)

CD54HC221

AKTIV

Monostabiler Dual-Multivibrator mit High Speed CMOS-Logik und Reset

Jetzt bestellen
Datenblatt

CD54HC221

AKTIV
Datenblatt Jetzt bestellen

Produktdetails

Number of channels 2 Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Technology family HC Input type Standard CMOS Output type Push-Pull Supply current (µA) 160 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 2 Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Technology family HC Input type Standard CMOS Output type Push-Pull Supply current (µA) 160 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92
  • Overriding RESET Terminates Output Pulse
  • Triggering from the Leading or Trailing Edge
  • Q and Q\ Buffered Outputs
  • Separate Resets
  • Wide Range of Output-Pulse Widths
  • Schmitt Trigger on B Inputs
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH

Data sheet acquired from Harris Semiconductor
  • Overriding RESET Terminates Output Pulse
  • Triggering from the Leading or Trailing Edge
  • Q and Q\ Buffered Outputs
  • Separate Resets
  • Wide Range of Output-Pulse Widths
  • Schmitt Trigger on B Inputs
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH

Data sheet acquired from Harris Semiconductor

The ’HC221 and CD74HCT221 are dual monostable multivibrators with reset. An external resistor (RX) and an external capacitor (CX) control the timing and the accuracy for the circuit. Adjustment of RX and CX provides a wide range of output pulse widths from the Q and Q\ terminals. Pulse triggering on the B input occurs at a particular voltage level and is not related to the rise and fall time of the trigger pulse.

Once triggered, the outputs are independent of further trigger inputs on A\ and B. The output pulse can be terminated by a LOW level on the Reset (R)\ pin. Trailing Edge triggering (A)\ and leading-edge-triggering (B) inputs are provided for triggering from either edge of the input pulse. On power up, the IC is reset. If either Mono is not used each input (on the unused device) must be terminated either high or low.

The minimum value of external resistance, RX, is typically 500. The minimum value of external capacitance, CX, is 0pF. The calculation for the pulse width is tW = 0.7 RXCX at VCC = 4.5V.

The ’HC221 and CD74HCT221 are dual monostable multivibrators with reset. An external resistor (RX) and an external capacitor (CX) control the timing and the accuracy for the circuit. Adjustment of RX and CX provides a wide range of output pulse widths from the Q and Q\ terminals. Pulse triggering on the B input occurs at a particular voltage level and is not related to the rise and fall time of the trigger pulse.

Once triggered, the outputs are independent of further trigger inputs on A\ and B. The output pulse can be terminated by a LOW level on the Reset (R)\ pin. Trailing Edge triggering (A)\ and leading-edge-triggering (B) inputs are provided for triggering from either edge of the input pulse. On power up, the IC is reset. If either Mono is not used each input (on the unused device) must be terminated either high or low.

The minimum value of external resistance, RX, is typically 500. The minimum value of external capacitance, CX, is 0pF. The calculation for the pulse width is tW = 0.7 RXCX at VCC = 4.5V.
filter Andere Multivibrator (One-Shot) suchen
Herunterladen Video mit Transkript ansehen Video

Technische Dokumentation

star =Von TI ausgewählte Top-Empfehlungen für dieses Produkt
Keine Ergebnisse gefunden. Bitte geben Sie einen anderen Begriff ein und versuchen Sie es erneut.
Alle anzeigen 16
Typ Titel Datum
* Data sheet CD54HC221, CD74HC221, CD74HCT221 datasheet (Rev. F) 16 Okt 2003
* SMD CD54HC221 SMD 5962-87805 21 Jun 2016
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Application note Designing With the SN74LVC1G123 Monostable Multivibrator (Rev. A) PDF | HTML 13 Mär 2020
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dez 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Okt 1996
Application note Live Insertion 01 Okt 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 Mai 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
CDIP (J) 16 Ultra Librarian
Es gelten die allgemeinen Geschäftsbedingungen von TI für Evaluierungsartikel.

Bestellen & Qualität

Beinhaltete Information:
  • RoHS
  • REACH
  • Bausteinkennzeichnung
  • Blei-Finish/Ball-Material
  • MSL-Rating / Spitzenrückfluss
  • MTBF-/FIT-Schätzungen
  • Materialinhalt
  • Qualifikationszusammenfassung
  • Kontinuierliches Zuverlässigkeitsmonitoring
Beinhaltete Information:
  • Werksstandort
  • Montagestandort

Support und Schulungen

TI E2E™-Foren mit technischem Support von TI-Ingenieuren

Alle Forenthemen auf Englisch anzeigen

Inhalte werden ohne Gewähr von TI und der Community bereitgestellt. Sie stellen keine Spezifikationen von TI dar. Siehe Nutzungsbedingungen.

Bei Fragen zu den Themen Qualität, Gehäuse oder Bestellung von TI-Produkten siehe TI-Support. ​​​​​​​​​​​​​​

Videos