CD74HC147

Name: CD74HC147
Brand: TI
SKU: CD74HC147
Price: 0.181 USD

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Highspeed-CMOS-Logik-Encoder mit 10 bis 4 Zeilenpriorität

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Datenblatt

document-pdfAcrobat CD54HC147, CD74HC147, CD74HCT147 datasheet (Rev. F) (Englisch)

CD74HC147

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Datenblatt

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Produktdetails

Technology family

HC

Function

Encoder

Configuration

10:4

Number of channels

1

Operating temperature range (°C)

-55 to 125

Rating

Catalog

Technology family

HC

Function

Encoder

Configuration

10:4

Number of channels

1

Operating temperature range (°C)

-55 to 125

Rating

Catalog

PDIP (N)

16

181.42 mm² 19.3 x 9.4

SOIC (D)

16

59.4 mm² 9.9 x 6

TSSOP (PW)

16

32 mm² 5 x 6.4

Buffered Inputs and Outputs
Typical Propagation Delay: 13ns at V_CC = 5V, C_L = 15pF, T_A = 25°C
Fanout (Over Temperature Range)
- Standard Outputs...10 LSTTL Loads
- Bus Driver Outputs...15 LSTTL Loads
Wide Operating Temperature Range... –55°C to 125°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l 1µA at V_OL, V_OH

Data sheet acquired from Harris Semiconductor

Buffered Inputs and Outputs
Typical Propagation Delay: 13ns at V_CC = 5V, C_L = 15pF, T_A = 25°C
Fanout (Over Temperature Range)
- Standard Outputs...10 LSTTL Loads
- Bus Driver Outputs...15 LSTTL Loads
Wide Operating Temperature Range... –55°C to 125°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l 1µA at V_OL, V_OH

Data sheet acquired from Harris Semiconductor

The ’HC147 and CD74HCT147 are high speed silicon-gate CMOS devices and are pin-compatible with low power Schottky TTL (LSTTL).

The ’HC147 and CD74HCT147 9-input priority encoders accept data from nine active LOW inputs (l₁ to l₉) and provide binary representation on the four active LOW inputs (Y0\ to Y3\). A priority is assigned to each input so that when two or more inputs are simultaneously active, the input with the highest priority is represented on the output, with input line l₉ having the highest priority.

These devices provide the 10-line to 4-line priority encoding function by use of the implied decimal "zero". The "zero" is encoded when all nine data inputs are HIGH, forcing all four outputs HIGH.

The ’HC147 and CD74HCT147 are high speed silicon-gate CMOS devices and are pin-compatible with low power Schottky TTL (LSTTL).

The ’HC147 and CD74HCT147 9-input priority encoders accept data from nine active LOW inputs (l₁ to l₉) and provide binary representation on the four active LOW inputs (Y0\ to Y3\). A priority is assigned to each input so that when two or more inputs are simultaneously active, the input with the highest priority is represented on the output, with input line l₉ having the highest priority.

These devices provide the 10-line to 4-line priority encoding function by use of the implied decimal "zero". The "zero" is encoded when all nine data inputs are HIGH, forcing all four outputs HIGH.

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Alle anzeigen 14

	Typ	Titel	Datum
*	Data sheet	CD54HC147, CD74HC147, CD74HCT147 datasheet (Rev. F)	30 Okt 2003
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)	26 Jul 2021
	Selection guide	Logic Guide (Rev. AB)	12 Jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 Dez 2015
	User guide	LOGIC Pocket Data Book (Rev. B)	16 Jan 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 Jul 2004
	User guide	Signal Switch Data Book (Rev. A)	14 Nov 2003
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	29 Aug 2002
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)	01 Jun 1997
	Application note	Designing With Logic (Rev. C)	01 Jun 1997
	Application note	Input and Output Characteristics of Digital Integrated Circuits	01 Okt 1996
	Application note	Live Insertion	01 Okt 1996
	Application note	SN54/74HCT CMOS Logic Family Applications and Restrictions	01 Mai 1996
	Application note	Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc	01 Apr 1996

Design und Entwicklung

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Evaluierungsplatine

14-24-LOGIC-EVM — Generisches Logikprodukt-Evaluierungsmodul für 14-polige bis 24-polige D-, DB-, DGV-, DW-, DYY-, NS-

Das 14-24-LOGIC-EVM-Evaluierungsmodul (EVM) ist für die Unterstützung aller Logikgeräte konzipiert, die sich in einem 14-Pin- bis 24-Pin-D-, DW-, DB-, NS-, PW-, DYY- oder DGV-Gehäuse befinden.

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Gehäuse	Pins	CAD-Symbole, Footprints und 3D-Modelle
PDIP (N)	16	Ultra Librarian
SOIC (D)	16	Ultra Librarian
TSSOP (PW)	16	Ultra Librarian

Es gelten die allgemeinen Geschäftsbedingungen von TI für Evaluierungsartikel.

CD74HC147

Highspeed-CMOS-Logik-Encoder mit 10 bis 4 Zeilenpriorität

CD74HC147

Produktdetails

Technische Dokumentation

Design und Entwicklung

14-24-LOGIC-EVM — Generisches Logikprodukt-Evaluierungsmodul für 14-polige bis 24-polige D-, DB-, DGV-, DW-, DYY-, NS-

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