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SN74AUP1T57

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SN74AUP1T57

AKTIV
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Produktdetails

Technology family AUP1T Number of channels 1 Vout (min) (V) 2.3 Vout (max) (V) 3.6 Data rate (max) (Mbps) 200 IOH (max) (mA) -4 IOL (max) (mA) 4 Supply current (max) (µA) 0.9 Features Over-voltage tolerant inputs, Partial power down (Ioff), Single supply, Voltage translation Input type Schmitt-Trigger Output type Balanced CMOS, Push-Pull Operating temperature range (°C) -40 to 85
Technology family AUP1T Number of channels 1 Vout (min) (V) 2.3 Vout (max) (V) 3.6 Data rate (max) (Mbps) 200 IOH (max) (mA) -4 IOL (max) (mA) 4 Supply current (max) (µA) 0.9 Features Over-voltage tolerant inputs, Partial power down (Ioff), Single supply, Voltage translation Input type Schmitt-Trigger Output type Balanced CMOS, Push-Pull Operating temperature range (°C) -40 to 85
SOT-23 (DBV) 6 8.12 mm² 2.9 x 2.8 SOT-SC70 (DCK) 6 4.2 mm² 2 x 2.1 USON (DRY) 6 1.45 mm² 1.45 x 1 X2SON (DSF) 6 1 mm² 1 x 1
  • Available in the Texas Instruments NanoStar™ Packages
  • Single-Supply Voltage Translator
  • 1.8 V to 3.3 V (at VCC = 3.3 V)
  • 2.5 V to 3.3 V (at VCC = 3.3 V)
  • 1.8 V to 2.5 V (at VCC = 2.5 V)
  • 3.3 V to 2.5 V (at VCC = 2.5 V)
  • Nine Configurable Gate Logic Functions
  • Schmitt-Trigger Inputs Reject Input Noise and Provide Better
    Output Signal Integrity
  • Ioff Supports Partial-Power-Down Mode With Low Leakage Current (0.5 µA)
  • Very Low Static and Dynamic Power Consumption
  • Pb-Free Packages Available: SON (DRY or DSF), SOT-23 (DBV),
    SC-70 (DCK), and NanoStar WCSP
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Related Devices: SN74AUP1T58, SN74AUP1T97, and SN74AUP1T98

NanoStar is a trademark of Texas Instruments.
  • Available in the Texas Instruments NanoStar™ Packages
  • Single-Supply Voltage Translator
  • 1.8 V to 3.3 V (at VCC = 3.3 V)
  • 2.5 V to 3.3 V (at VCC = 3.3 V)
  • 1.8 V to 2.5 V (at VCC = 2.5 V)
  • 3.3 V to 2.5 V (at VCC = 2.5 V)
  • Nine Configurable Gate Logic Functions
  • Schmitt-Trigger Inputs Reject Input Noise and Provide Better
    Output Signal Integrity
  • Ioff Supports Partial-Power-Down Mode With Low Leakage Current (0.5 µA)
  • Very Low Static and Dynamic Power Consumption
  • Pb-Free Packages Available: SON (DRY or DSF), SOT-23 (DBV),
    SC-70 (DCK), and NanoStar WCSP
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Related Devices: SN74AUP1T58, SN74AUP1T97, and SN74AUP1T98

NanoStar is a trademark of Texas Instruments.

AUP technology is the industry’s lowest-power logic technology designed for use in battery-operated or battery backed-up equipment. The SN74AUP1T57 is designed for logic-level translation applications with input switching levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCC supply.

The wide VCC range of 2.3 V to 3.6 V allows the possibility of battery voltage drop during system operation and ensures normal operation between this range.

Schmitt-trigger inputs (VT = 210 mV between positive and negative input transitions) offer improved noise immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition.

The SN74AUP1T57 can be easily configured to perform a required gate function by connecting A, B, and C inputs to VCC or ground (see Function Selection table). Up to nine commonly used logic gate functions can be performed.

Ioff is a feature that allows for powered-down conditions (VCC = 0 V) and is important in portable and mobile applications. When VCC = 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of the device. No damage occurs to the device under these conditions.

The SN74AUP1T57 is designed with optimized current-drive capability of 4 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.

NanoStar package technology is a major breakthrough in IC packaging concepts, using the die as the package.

AUP technology is the industry’s lowest-power logic technology designed for use in battery-operated or battery backed-up equipment. The SN74AUP1T57 is designed for logic-level translation applications with input switching levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCC supply.

The wide VCC range of 2.3 V to 3.6 V allows the possibility of battery voltage drop during system operation and ensures normal operation between this range.

Schmitt-trigger inputs (VT = 210 mV between positive and negative input transitions) offer improved noise immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition.

The SN74AUP1T57 can be easily configured to perform a required gate function by connecting A, B, and C inputs to VCC or ground (see Function Selection table). Up to nine commonly used logic gate functions can be performed.

Ioff is a feature that allows for powered-down conditions (VCC = 0 V) and is important in portable and mobile applications. When VCC = 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of the device. No damage occurs to the device under these conditions.

The SN74AUP1T57 is designed with optimized current-drive capability of 4 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.

NanoStar package technology is a major breakthrough in IC packaging concepts, using the die as the package.
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Typ Titel Datum
* Data sheet SN74AUP1T57 Single-Supply Voltage-Level Translator With Configurable Functions datasheet (Rev. G) 07 Mai 2010
Selection guide Voltage Translation Buying Guide (Rev. A) 15 Apr 2021
Application brief Understanding Schmitt Triggers (Rev. A) PDF | HTML 22 Mai 2019

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