SN74LV1T126-Q1

Name: SN74LV1T126-Q1
Brand: TI
SKU: SN74LV1T126-Q1
Price: 0.142 USD

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Datenblatt

document-pdfAcrobat SN74LV1T126-Q1 AutomotiveSingle Buffer Gate With 3-State Output and Integrated Translation datasheet (Rev. A) (Englisch) PDF | HTML

SN74LV1T126-Q1

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Datenblatt

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Produktdetails

Technology family

LV1T

Applications

GPIO, SPI

Bits (#)

1

Configuration

1 Ch A to B 0 Ch B to A

High input voltage (min) (V)

1

High input voltage (max) (V)

5.5

Vout (min) (V)

1.65

Vout (max) (V)

5.5

Data rate (max) (Mbps)

100

IOH (max) (mA)

-8

IOL (max) (mA)

8

Features

Balanced outputs, Single supply

Input type

TTL-Compatible CMOS

Output type

3-State, Balanced CMOS

Rating

Automotive

Operating temperature range (°C)

-40 to 125

Technology family

LV1T

Applications

GPIO, SPI

Bits (#)

1

Configuration

1 Ch A to B 0 Ch B to A

High input voltage (min) (V)

1

High input voltage (max) (V)

5.5

Vout (min) (V)

1.65

Vout (max) (V)

5.5

Data rate (max) (Mbps)

100

IOH (max) (mA)

-8

IOL (max) (mA)

8

Features

Balanced outputs, Single supply

Input type

TTL-Compatible CMOS

Output type

3-State, Balanced CMOS

Rating

Automotive

Operating temperature range (°C)

-40 to 125

SOT-23 (DBV)

5

8.12 mm² 2.9 x 2.8

SOT-SC70 (DCK)

5

4.2 mm² 2 x 2.1

AEC-Q100 qualified for automotive applications:
- Device temperature grade 1: -40°C to +125°C
- Device HBM ESD classification level 2
- Device CDM ESD classification level C4B
Wide operating range of 1.8 V to 5.5 V
Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
- Up translation:
  - 1.2 V to 1.8 V
  - 1.5 V to 2.5 V
  - 1.8 V to 3.3 V
  - 3.3 V to 5.0 V
- Down translation:
  - 5.0 V, 3.3 V, 2.5 V to 1.8 V
  - 5.0 V, 3.3 V to 2.5 V
  - 5.0 V to 3.3 V
5.5-V tolerant input pins
Supports standard pinouts
Up to 150 Mbps with 5-V or 3.3-V V CC
Latch-up performance exceeds 250 mA per JESD 17

AEC-Q100 qualified for automotive applications:
- Device temperature grade 1: -40°C to +125°C
- Device HBM ESD classification level 2
- Device CDM ESD classification level C4B
Wide operating range of 1.8 V to 5.5 V
Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
- Up translation:
  - 1.2 V to 1.8 V
  - 1.5 V to 2.5 V
  - 1.8 V to 3.3 V
  - 3.3 V to 5.0 V
- Down translation:
  - 5.0 V, 3.3 V, 2.5 V to 1.8 V
  - 5.0 V, 3.3 V to 2.5 V
  - 5.0 V to 3.3 V
5.5-V tolerant input pins
Supports standard pinouts
Up to 150 Mbps with 5-V or 3.3-V V CC
Latch-up performance exceeds 250 mA per JESD 17

The SN74LV1T126-Q1 is a single buffer gate with 3-state outputs and integrated voltage translation. This buffer performs the Boolean function Y = A in positive logic. The outputs can be placed into a Hi-Z state by applying a Low on the OE pin. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).

The SN74LV1T126-Q1 is a single buffer gate with 3-state outputs and integrated voltage translation. This buffer performs the Boolean function Y = A in positive logic. The outputs can be placed into a Hi-Z state by applying a Low on the OE pin. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).

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	Typ	Titel		Datum
*	Data sheet	SN74LV1T126-Q1 AutomotiveSingle Buffer Gate With 3-State Output and Integrated Translation datasheet (Rev. A)	PDF \| HTML	16 Nov 2023
	Application note	Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators	PDF \| HTML	02 Okt 2024
	Application note	Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators	PDF \| HTML	12 Jul 2024
	Application note	Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A)	PDF \| HTML	03 Jul 2024

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SOT-SC70 (DCK)	5	Ultra Librarian

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SN74LV1T126-Q1

Einzelnes Puffer-Gate für Einfachstromversorgung mit Tri-State-Ausgang mit Active High-aktiv, für di

SN74LV1T126-Q1

Produktdetails

Technische Dokumentation

Design und Entwicklung

5-8-LOGIC-EVM — Generisches Logik-Evaluierungsmodul für 5- bis 8-polige DCK-, DCT-, DCU-, DRL- und DBV-Gehäuse

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