SN74LVC1G80-Q1

Name: SN74LVC1G80-Q1
Brand: TI
SKU: SN74LVC1G80-Q1
Price: 0.083 USD

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Einzelflipflop (Typ D) mit positiver Flankensteuerung für die Automobilindustrie

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Datenblatt

document-pdfAcrobat SN74LVC1G80-Q1 Single Positive-Edge-Triggered D-Type Flip-Flop datasheet (Englisch) PDF | HTML

SN74LVC1G80-Q1

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Datenblatt

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Produktdetails

Number of channels

1

Technology family

LVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

5.5

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

150

IOL (max) (mA)

32

IOH (max) (mA)

-32

Supply current (max) (µA)

10

Features

Balanced outputs, Over-voltage tolerant inputs

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Number of channels

1

Technology family

LVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

5.5

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

150

IOL (max) (mA)

32

IOH (max) (mA)

-32

Supply current (max) (µA)

10

Features

Balanced outputs, Over-voltage tolerant inputs

Operating temperature range (°C)

-40 to 125

Rating

Automotive

SOT-SC70 (DCK)

5

4.2 mm² 2 x 2.1

Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
- ±4000-V Human-Body Model (HBM) ESD Classification Level 3A
- ±1000-V Charged-Device Model (CDM) ESD Classification Level C5
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Supports Down Translation to V_CC
Maximum t_pd of 6 ns at 3.3 V
Low Power Consumption, 10-µA Max I_CC
±24-mA Output Drive at 3.3 V
I_off supports Partial-Power-Down Mode and Back-Drive Protection

Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
- ±4000-V Human-Body Model (HBM) ESD Classification Level 3A
- ±1000-V Charged-Device Model (CDM) ESD Classification Level C5
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Supports Down Translation to V_CC
Maximum t_pd of 6 ns at 3.3 V
Low Power Consumption, 10-µA Max I_CC
±24-mA Output Drive at 3.3 V
I_off supports Partial-Power-Down Mode and Back-Drive Protection

The SN74LVC1G80-Q1 device is an automotive AEC-Q100 qualified, single positive-edge-triggered D-type flip-flop that is designed for 1.65-V to 5.5-V V_CC operation.

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

The SN74LVC1G80-Q1 device is an automotive AEC-Q100 qualified, single positive-edge-triggered D-type flip-flop that is designed for 1.65-V to 5.5-V V_CC operation.

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

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	Typ	Titel		Datum
*	Data sheet	SN74LVC1G80-Q1 Single Positive-Edge-Triggered D-Type Flip-Flop datasheet	PDF \| HTML	07 Apr 2017
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	Selection guide	Logic Guide (Rev. AB)		12 Jun 2017
	Application note	How to Select Little Logic (Rev. A)		26 Jul 2016
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		02 Dez 2015
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	Product overview	Design Summary for WCSP Little Logic (Rev. B)		04 Nov 2004
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		08 Jul 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)		22 Jun 2004
	User guide	Signal Switch Data Book (Rev. A)		14 Nov 2003
	Application note	Use of the CMOS Unbuffered Inverter in Oscillator Circuits		06 Nov 2003
	User guide	LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)		18 Dez 2002
	Application note	Texas Instruments Little Logic Application Report		01 Nov 2002
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	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices		01 Dez 1997
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	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)		01 Jun 1997
	Application note	LVC Characterization Information		01 Dez 1996
	Application note	Input and Output Characteristics of Digital Integrated Circuits		01 Okt 1996
	Application note	Live Insertion		01 Okt 1996
	Design guide	Low-Voltage Logic (LVC) Designer's Guide		01 Sep 1996
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Design und Entwicklung

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