SN74LVC2GU04

Name: SN74LVC2GU04
Brand: TI
SKU: SN74LVC2GU04
Price: 0.205 USD

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2-Kanal-Wechselrichter, 1,65 V bis 5,5 V

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Datenblatt

document-pdfAcrobat Dual Inverter Gate--SN74LVC2GU04 datasheet (Rev. N) (Englisch)

SN74LVC2GU04

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Datenblatt

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Produktdetails

Technology family

LVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

5.5

Number of channels

IOL (max) (mA)

IOH (max) (mA)

-32

Supply current (max) (µA)

Input type

Standard CMOS

Output type

Push-Pull

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Unbuffered, Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Technology family

LVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

5.5

Number of channels

IOL (max) (mA)

IOH (max) (mA)

-32

Supply current (max) (µA)

Input type

Standard CMOS

Output type

Push-Pull

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Unbuffered, Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

DSBGA (YZP)

2.1875 mm² 1.75 x 1.25

SOT-23 (DBV)

8.12 mm² 2.9 x 2.8

SOT-SC70 (DCK)

4.2 mm² 2 x 2.1

Available in the Texas Instruments NanoFree Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 3.7 ns at 3.3 V
Low Power Consumption, 10-µA Max I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Can Be Used as a Down Translator to Translate Inputs From a Max of 5.5 V Down to the V_CC Level
Unbuffered Outputs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Available in the Texas Instruments NanoFree Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 3.7 ns at 3.3 V
Low Power Consumption, 10-µA Max I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Can Be Used as a Down Translator to Translate Inputs From a Max of 5.5 V Down to the V_CC Level
Unbuffered Outputs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

This dual inverter is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC2GU04 device contains two inverters with unbuffered outputs and performs the Boolean function Y = A.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This dual inverter is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC2GU04 device contains two inverters with unbuffered outputs and performs the Boolean function Y = A.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

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Alle anzeigen 28

	Typ	Titel		Datum
*	Data sheet	Dual Inverter Gate--SN74LVC2GU04 datasheet (Rev. N)		12 Dez 2013
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)		26 Jul 2021
	Application brief	Generate a Clock Signal from a Crystal Oscillator	PDF \| HTML	08 Okt 2020
	Selection guide	Little Logic Guide 2018 (Rev. G)		06 Jul 2018
	Selection guide	Logic Guide (Rev. AB)		12 Jun 2017
	Application note	How to Select Little Logic (Rev. A)		26 Jul 2016
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		02 Dez 2015
	User guide	LOGIC Pocket Data Book (Rev. B)		16 Jan 2007
	Product overview	Design Summary for WCSP Little Logic (Rev. B)		04 Nov 2004
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		08 Jul 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)		22 Jun 2004
	User guide	Signal Switch Data Book (Rev. A)		14 Nov 2003
	Application note	Use of the CMOS Unbuffered Inverter in Oscillator Circuits		06 Nov 2003
	User guide	LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)		18 Dez 2002
	Application note	Texas Instruments Little Logic Application Report		01 Nov 2002
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		29 Aug 2002
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards		13 Jun 2002
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)		22 Mai 2002
	Application note	Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices		10 Mai 2002
	More literature	STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS		27 Mär 2002
	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices		01 Dez 1997
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)		01 Aug 1997
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)		01 Jun 1997
	Application note	LVC Characterization Information		01 Dez 1996
	Application note	Input and Output Characteristics of Digital Integrated Circuits		01 Okt 1996
	Application note	Live Insertion		01 Okt 1996
	Design guide	Low-Voltage Logic (LVC) Designer's Guide		01 Sep 1996
	Application note	Understanding Advanced Bus-Interface Products Design Guide		01 Mai 1996

Design und Entwicklung

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