Startseite Mikrocontroller (MCUs) & Prozessoren Digitale Signalprozessoren (DSPs)
Startseite
Mikrocontroller (MCUs) & Prozessoren
Digitale Signalprozessoren (DSPs)

TMS320VC5407

AKTIV

Digitaler Signalprozessor

Jetzt bestellen
Datenblatt

TMS320VC5407

AKTIV
Datenblatt Jetzt bestellen

Produktdetails

DSP type 1 C54x DSP (max) (MHz) 120 CPU 16-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) 0 to 0
DSP type 1 C54x DSP (max) (MHz) 120 CPU 16-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) 0 to 0
LQFP (PGE) 144 484 mm² 22 x 22
  • Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
  • 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
  • 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
  • Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
  • Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
  • Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
  • Data Bus With a Bus Holder Feature
  • Extended Addressing Mode for 8M × 16-Bit Maximum Addressable External Program Space
  • On-Chip ROM
    • 128K × 16-Bit (5407) Configured for Program Memory
    • 64K × 16-Bit (5404) Configured for Program Memory
  • On-Chip RAM
    • 40K × 16-Bit (5407) Composed of Five Blocks of 8K × 16-Bit On-Chip Dual-Access Program/Data RAM
    • 16K x 16-Bit (5404) Composed of Two Blocks of 8K × 16-Bit On-Chip Dual-Access Program/Data RAM
  • Enhanced External Parallel Interface (XIO2)
  • Single-Instruction-Repeat and Block-Repeat Operations for Program Code
  • Block-Memory-Move Instructions for Better Program and Data Management
  • Instructions With a 32-Bit Long Word Operand
  • Instructions With Two- or Three-Operand Reads
  • Arithmetic Instructions With Parallel Store and Parallel Load
  • Conditional Store Instructions
  • Fast Return From Interrupt
  • On-Chip Peripherals
    • Software-Programmable Wait-State Generator and Programmable Bank-Switching
    • On-Chip Programmable Phase-Locked Loop (PLL) Clock Generator With External Clock Source
    • Two 16-Bit Timers
    • Six-Channel Direct Memory Access (DMA) Controller
    • Three Multichannel Buffered Serial Ports (McBSPs)
    • 8/16-Bit Enhanced Parallel Host-Port Interface (HPI8/16)
    • Universal Asynchronous Receiver/Transmitter (UART) With Integrated Baud Rate Generator
  • Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
  • CLKOUT Off Control to Disable CLKOUT
  • On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG) Boundary Scan Logic
  • 144-Pin Ball Grid Array (BGA) (GGU Suffix)
  • 144-Pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
  • 8.33-ns Single-Cycle Fixed-Point Instruction Execution Time (120 MIPS)
  • 3.3-V I/O Supply Voltage
  • 1.5-V Core Supply Voltage

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
All trademarks are the property of their respective owners.
TMS320C54x is a trademark of Texas Instruments.
  • Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
  • 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
  • 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
  • Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
  • Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
  • Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
  • Data Bus With a Bus Holder Feature
  • Extended Addressing Mode for 8M × 16-Bit Maximum Addressable External Program Space
  • On-Chip ROM
    • 128K × 16-Bit (5407) Configured for Program Memory
    • 64K × 16-Bit (5404) Configured for Program Memory
  • On-Chip RAM
    • 40K × 16-Bit (5407) Composed of Five Blocks of 8K × 16-Bit On-Chip Dual-Access Program/Data RAM
    • 16K x 16-Bit (5404) Composed of Two Blocks of 8K × 16-Bit On-Chip Dual-Access Program/Data RAM
  • Enhanced External Parallel Interface (XIO2)
  • Single-Instruction-Repeat and Block-Repeat Operations for Program Code
  • Block-Memory-Move Instructions for Better Program and Data Management
  • Instructions With a 32-Bit Long Word Operand
  • Instructions With Two- or Three-Operand Reads
  • Arithmetic Instructions With Parallel Store and Parallel Load
  • Conditional Store Instructions
  • Fast Return From Interrupt
  • On-Chip Peripherals
    • Software-Programmable Wait-State Generator and Programmable Bank-Switching
    • On-Chip Programmable Phase-Locked Loop (PLL) Clock Generator With External Clock Source
    • Two 16-Bit Timers
    • Six-Channel Direct Memory Access (DMA) Controller
    • Three Multichannel Buffered Serial Ports (McBSPs)
    • 8/16-Bit Enhanced Parallel Host-Port Interface (HPI8/16)
    • Universal Asynchronous Receiver/Transmitter (UART) With Integrated Baud Rate Generator
  • Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
  • CLKOUT Off Control to Disable CLKOUT
  • On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG) Boundary Scan Logic
  • 144-Pin Ball Grid Array (BGA) (GGU Suffix)
  • 144-Pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
  • 8.33-ns Single-Cycle Fixed-Point Instruction Execution Time (120 MIPS)
  • 3.3-V I/O Supply Voltage
  • 1.5-V Core Supply Voltage

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
All trademarks are the property of their respective owners.
TMS320C54x is a trademark of Texas Instruments.

This data manual discusses features and specifications of the TMS320VC5407 and TMS320VC5404 (hereafter referred to as the 5407/5404 unless otherwise specified) digital signal processors (DSPs). The 5407 and 5404 are essentially the same device except for differences in their memory maps.

This section lists the pin assignments and describes the function of each pin. This data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data about the available packaging.

NOTE: This data sheet is designed to be used in conjunction with the TMS320C5000 DSP Family Functional Overview (literature number SPRU307).

The 5407/5404 are based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. These processors provide an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of these DSPs is a highly specialized instruction set.

Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. These DSPs also include the control mechanisms to manage interrupts, repeated operations, and function calls.

This data manual discusses features and specifications of the TMS320VC5407 and TMS320VC5404 (hereafter referred to as the 5407/5404 unless otherwise specified) digital signal processors (DSPs). The 5407 and 5404 are essentially the same device except for differences in their memory maps.

This section lists the pin assignments and describes the function of each pin. This data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data about the available packaging.

NOTE: This data sheet is designed to be used in conjunction with the TMS320C5000 DSP Family Functional Overview (literature number SPRU307).

The 5407/5404 are based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. These processors provide an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of these DSPs is a highly specialized instruction set.

Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. These DSPs also include the control mechanisms to manage interrupts, repeated operations, and function calls.
filter Andere Digitale Signalprozessoren (DSPs) suchen
Herunterladen Video mit Transkript ansehen Video
Keine Designunterstützung von TI verfügbar

Für dieses Produkt gibt es keine laufende Designunterstützung von TI für neue Projekte wie neue Inhalte oder Software-Updates. Wenn verfügbar, finden Sie im Produktordner relevante Begleitmaterialien, Software und Tools. Sie können auch in den TI E2ETM Supportforen nach archivierten Informationen suchen.

Technische Dokumentation

star =Von TI ausgewählte Top-Empfehlungen für dieses Produkt
Keine Ergebnisse gefunden. Bitte geben Sie einen anderen Begriff ein und versuchen Sie es erneut.
Alle anzeigen 6
Typ Titel Datum
* Data sheet TMS320VC5407/TMS320VC5404 Fixed-Point Digital Signal Processors datasheet (Rev. E) 20 Okt 2008
User guide TMS320C54x Chip Support Library API Reference Guide (Rev. D) 05 Mai 2003
User guide TMS320C54x DSP CPU and Peripherals Reference Set Volume 1 (Rev. G) 31 Mär 2001
User guide TMS320C54x DSP Algebraic Instruction Set Reference Set Volume 3 (Rev. C) 31 Jan 2001
User guide TMS320C54x DSP Mnemonic Instruction Set Reference Set Volume 2 (Rev. C) 31 Jan 2001
User guide TMS320C54x DSP Applications Guide Reference Set Volume 4 01 Okt 1996

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Debug-Tastkopf

TMDSEMU560V2STM-U — XDS560v2 System-Trace-USB-Debug-Tastkopf

Der XDS560v2 ist die leistungsstärkste Debug-Sonde aus der XDS560™ Familie von Debug-Sonden und unterstützt sowohl den traditionellen JTAG-Standard (IEEE1149.1) als auch cJTAG (IEEE1149.7).  Bitte beachten: Diese Lösung unterstützt kein Serial Wire Debug (SWD).

Alle XDS-Debug-Tastköpfe unterstützen (...)

Nicht verfügbar auf TI.com
Debug-Tastkopf

TMDSEMU560V2STM-UE — XDS560v2 System-Trace-USB-und Ethernet-Debug-Tastkopf

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

Nicht verfügbar auf TI.com
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
LQFP (PGE) 144 Ultra Librarian
Es gelten die allgemeinen Geschäftsbedingungen von TI für Evaluierungsartikel.

Bestellen & Qualität

Beinhaltete Information:
  • RoHS
  • REACH
  • Bausteinkennzeichnung
  • Blei-Finish/Ball-Material
  • MSL-Rating / Spitzenrückfluss
  • MTBF-/FIT-Schätzungen
  • Materialinhalt
  • Qualifikationszusammenfassung
  • Kontinuierliches Zuverlässigkeitsmonitoring
Beinhaltete Information:
  • Werksstandort
  • Montagestandort

Empfohlene Produkte können Parameter, Evaluierungsmodule oder Referenzdesigns zu diesem TI-Produkt beinhalten.

Support und Schulungen

TI E2E™-Foren mit technischem Support von TI-Ingenieuren

Alle Forenthemen auf Englisch anzeigen

Inhalte werden ohne Gewähr von TI und der Community bereitgestellt. Sie stellen keine Spezifikationen von TI dar. Siehe Nutzungsbedingungen.

Bei Fragen zu den Themen Qualität, Gehäuse oder Bestellung von TI-Produkten siehe TI-Support. ​​​​​​​​​​​​​​

Videos