TMS320VC5416

Name: TMS320VC5416
Brand: TI
SKU: TMS320VC5416
Price: 26.078 USD

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Datenblatt

document-pdfAcrobat TMS320VC5416 Fixed-Point Digital Signal Processor datasheet (Rev. P) (Englisch)

Fehlerverzeichnis

document-pdfAcrobat
TMS320VC5416 MicroStar BGA Discontinued and Redesigned (Englisch)
document-pdfAcrobat
TMS320VC5416 Digital Signal Processor Silicon Errata (Rev. F) (Englisch)

TMS320VC5416

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Datenblatt

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Produktdetails

DSP type

1 C54x

DSP (max) (MHz)

120, 160

CPU

16-bit

Rating

Catalog

Operating temperature range (°C)

-40 to 85

DSP type

1 C54x

DSP (max) (MHz)

120, 160

CPU

16-bit

Rating

Catalog

Operating temperature range (°C)

-40 to 85

LQFP (PGE)

144

484 mm² 22 x 22

NFBGA (GWS)

144

144 mm² 12 x 12

NFBGA (ZWS)

144

144 mm² 12 x 12

Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
17- ×17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
Data Bus With a Bus Holder Feature
Extended Addressing Mode for 8M × 16-Bit Maximum Addressable External Program Space
128K × 16-Bit On-Chip RAM Composed of:
- Eight Blocks of 8K × 16-Bit On-Chip Dual-Access Program/Data RAM
- Eight Blocks of 8K × 16-Bit On-Chip Single-Access Program RAM
16K × 16-Bit On-Chip ROM Configured for Program Memory
Enhanced External Parallel Interface (XIO2)
Single-Instruction-Repeat and Block-Repeat Operations for Program Code
Block-Memory-Move Instructions for Better Program and Data Management
Instructions With a 32-Bit Long Word Operand
Instructions With Two- or Three-Operand Reads
Arithmetic Instructions With Parallel Store and Parallel Load
Conditional Store Instructions
Fast Return From Interrupt
On-Chip Peripherals
- Software-Programmable Wait-State Generator and Programmable Bank-Switching
- On-Chip Programmable Phase-Locked Loop (PLL) Clock Generator With External Clock Source
- One 16-Bit Timer
- Six-Channel Direct Memory Access (DMA) Controller
- Three Multichannel Buffered Serial Ports (McBSPs)
- 8/16-Bit Enhanced Parallel Host-Port Interface (HPI8/16)
Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG) Boundary Scan Logic⁽¹⁾
144-Pin Ball Grid Array (BGA) (GGU Suffix)
144-Pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
6.25-ns Single-Cycle Fixed-Point Instruction Execution Time (160 MIPS)
8.33-ns Single-Cycle Fixed-Point Instruction Execution Time (120 MIPS)
3.3-V I/O Supply Voltage (160 and 120 MIPS)
1.6-V Core Supply Voltage (160 MIPS)
1.5-V Core Supply Voltage (120 MIPS)

⁽¹⁾IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
NOTE: This data manual is designed to be used in conjunction with the TMS320C54x™ DSP Functional Overview (literature number SPRU307).
TMS320C54x, TMS320 are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.

Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
17- ×17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
Data Bus With a Bus Holder Feature
Extended Addressing Mode for 8M × 16-Bit Maximum Addressable External Program Space
128K × 16-Bit On-Chip RAM Composed of:
- Eight Blocks of 8K × 16-Bit On-Chip Dual-Access Program/Data RAM
- Eight Blocks of 8K × 16-Bit On-Chip Single-Access Program RAM
16K × 16-Bit On-Chip ROM Configured for Program Memory
Enhanced External Parallel Interface (XIO2)
Single-Instruction-Repeat and Block-Repeat Operations for Program Code
Block-Memory-Move Instructions for Better Program and Data Management
Instructions With a 32-Bit Long Word Operand
Instructions With Two- or Three-Operand Reads
Arithmetic Instructions With Parallel Store and Parallel Load
Conditional Store Instructions
Fast Return From Interrupt
On-Chip Peripherals
- Software-Programmable Wait-State Generator and Programmable Bank-Switching
- On-Chip Programmable Phase-Locked Loop (PLL) Clock Generator With External Clock Source
- One 16-Bit Timer
- Six-Channel Direct Memory Access (DMA) Controller
- Three Multichannel Buffered Serial Ports (McBSPs)
- 8/16-Bit Enhanced Parallel Host-Port Interface (HPI8/16)
Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG) Boundary Scan Logic⁽¹⁾
144-Pin Ball Grid Array (BGA) (GGU Suffix)
144-Pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix)
6.25-ns Single-Cycle Fixed-Point Instruction Execution Time (160 MIPS)
8.33-ns Single-Cycle Fixed-Point Instruction Execution Time (120 MIPS)
3.3-V I/O Supply Voltage (160 and 120 MIPS)
1.6-V Core Supply Voltage (160 MIPS)
1.5-V Core Supply Voltage (120 MIPS)

⁽¹⁾IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
NOTE: This data manual is designed to be used in conjunction with the TMS320C54x™ DSP Functional Overview (literature number SPRU307).
TMS320C54x, TMS320 are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.

The TMS320VC5416 fixed-point, digital signal processor (DSP) (hereafter referred to as the 5416 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.

Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. The device also includes the control mechanisms to manage interrupts, repeated operations, and function calls.

The TMS320VC5416 fixed-point, digital signal processor (DSP) (hereafter referred to as the 5416 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.

Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. The device also includes the control mechanisms to manage interrupts, repeated operations, and function calls.

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Technische Dokumentation

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Alle anzeigen 11

	Typ	Titel	Datum
*	Data sheet	TMS320VC5416 Fixed-Point Digital Signal Processor datasheet (Rev. P)	13 Okt 2008
*	Errata	TMS320VC5416 MicroStar BGA Discontinued and Redesigned	20 Mai 2020
*	Errata	TMS320VC5416 Digital Signal Processor Silicon Errata (Rev. F)	31 Jan 2006
	Application note	TMS320VC5402A/VC5409A/VC5410A/VC5416 Bootloader (Rev. F)	27 Jun 2006
	Application note	Interface TSC Through McBSP	28 Okt 2004
	User guide	TMS320C54x Chip Support Library API Reference Guide (Rev. D)	05 Mai 2003
	Application note	Interfacing the ADS8361 to the TMS320VC5416 DSP	05 Dez 2002
	User guide	TMS320C54x DSP CPU and Peripherals Reference Set Volume 1 (Rev. G)	31 Mär 2001
	User guide	TMS320C54x DSP Algebraic Instruction Set Reference Set Volume 3 (Rev. C)	31 Jan 2001
	User guide	TMS320C54x DSP Mnemonic Instruction Set Reference Set Volume 2 (Rev. C)	31 Jan 2001
	User guide	TMS320C54x DSP Applications Guide Reference Set Volume 4	01 Okt 1996

Design und Entwicklung

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Debug-Tastkopf

TMDSEMU560V2STM-U — XDS560v2 System-Trace-USB-Debug-Tastkopf

Der XDS560v2 ist die leistungsstärkste Debug-Sonde aus der XDS560™ Familie von Debug-Sonden und unterstützt sowohl den traditionellen JTAG-Standard (IEEE1149.1) als auch cJTAG (IEEE1149.7). Bitte beachten: Diese Lösung unterstützt kein Serial Wire Debug (SWD).

Alle XDS-Debug-Tastköpfe unterstützen (...)

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Debug-Tastkopf

TMDSEMU560V2STM-UE — XDS560v2 System-Trace-USB-und Ethernet-Debug-Tastkopf

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)