CD4541B

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Temporizador programable CMOS - Tipo de alta tensión (20 V nominales)

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document-pdfAcrobat CD4541B datasheet (Rev. E) (Inglés)

CD4541B

ACTIVO

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Detalles del producto

Technology family

CD4000

Bits (#)

1

Rating

Catalog

Operating temperature range (°C)

-55 to 125

Technology family

CD4000

Bits (#)

1

Rating

Catalog

Operating temperature range (°C)

-55 to 125

PDIP (N)

14

181.42 mm² 19.3 x 9.4

SOIC (D)

14

51.9 mm² 8.65 x 6

SOP (NS)

14

79.56 mm² 10.2 x 7.8

TSSOP (PW)

14

32 mm² 5 x 6.4

Low Symmetrical Output Resistance, Typically 100 at V_DD = 15V
Built-In Low-Power RC Oscillator
Oscillator Frequency Range . . . DC to 100kHz
External Clock (Applied to Pin 3) can be Used Instead of Oscillator
Operates as 2^N Frequency Divider or as a Single-Transition Timer
Q/Q\ Select Provides Output Logic Level Flexibility
AUTO or MASTER RESET Disables Oscillator During Reset to Reduce Power Dissipation
Operates With Very Slow Clock Rise and Fall Times
Capable of Driving Six Low Power TTL Loads, Three Low-Power Schottky Loads, or Six HTL Loads Over the Rated Temperature Range
Symmetrical Output Characteristics
100% Tested for Quiescent Current at 20V
5V, 10V, and 15V Parametric Ratings
Meets All Requirements of JEDEC Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"

Data sheet acquired from Harris Semiconductor

Low Symmetrical Output Resistance, Typically 100 at V_DD = 15V
Built-In Low-Power RC Oscillator
Oscillator Frequency Range . . . DC to 100kHz
External Clock (Applied to Pin 3) can be Used Instead of Oscillator
Operates as 2^N Frequency Divider or as a Single-Transition Timer
Q/Q\ Select Provides Output Logic Level Flexibility
AUTO or MASTER RESET Disables Oscillator During Reset to Reduce Power Dissipation
Operates With Very Slow Clock Rise and Fall Times
Capable of Driving Six Low Power TTL Loads, Three Low-Power Schottky Loads, or Six HTL Loads Over the Rated Temperature Range
Symmetrical Output Characteristics
100% Tested for Quiescent Current at 20V
5V, 10V, and 15V Parametric Ratings
Meets All Requirements of JEDEC Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"

Data sheet acquired from Harris Semiconductor

CD4541B programmable timer consists of a 16-stage binary counter, an oscillator that is controlled by external R-C components (2 resistors and a capacitor), an automatic power-on reset circuit, and output control logic. The counter increments on positive-edge clock transitions and can also be reset via the MASTER RESET input.

The output from this timer is the Q or Q\ output from the 8th, 10th, 13th, or 16th counter stage. The desired stage is chosen using time-select inputs A and B (see Frequency Select Table).

The output is available in either of two modes selectable via the MODE input, pin 10 (see Truth Table). When this MODE input is a logic "1", the output will be a continuous square wave having a frequency equal to the oscillator frequency divided by 2^N. With the MODE input set to logic "0" and after a MASTER RESET is initiated, the output (assuming Q output has been selected) changes from a low to a high state after 2^N-1 counts and remains in that state until another MASTER RESET pulse is applied or the MODE input is set to a logic "1".

Timing is initialized by setting the AUTO RESET input (pin 5) to logic "0" and turning power on. If pin 5 is set to logic "1", the AUTO RESET circuit is disabled and counting will not start until after a positive MASTER RESET pulse is applied and returns to a low level. The AUTO RESET consumes an appreciable amount of power and should not be used if low-power operation is desired. For reliable automatic power-on reset, V_DD should be greater than 5V.

The RC oscillator, shown in Figure 2, oscillates with a frequency determined by the RC network and is calculated using:

Where f is between 1kHz and 100kHz and R_S and 2R_TC.

CD4541B programmable timer consists of a 16-stage binary counter, an oscillator that is controlled by external R-C components (2 resistors and a capacitor), an automatic power-on reset circuit, and output control logic. The counter increments on positive-edge clock transitions and can also be reset via the MASTER RESET input.

The output from this timer is the Q or Q\ output from the 8th, 10th, 13th, or 16th counter stage. The desired stage is chosen using time-select inputs A and B (see Frequency Select Table).

The output is available in either of two modes selectable via the MODE input, pin 10 (see Truth Table). When this MODE input is a logic "1", the output will be a continuous square wave having a frequency equal to the oscillator frequency divided by 2^N. With the MODE input set to logic "0" and after a MASTER RESET is initiated, the output (assuming Q output has been selected) changes from a low to a high state after 2^N-1 counts and remains in that state until another MASTER RESET pulse is applied or the MODE input is set to a logic "1".

Timing is initialized by setting the AUTO RESET input (pin 5) to logic "0" and turning power on. If pin 5 is set to logic "1", the AUTO RESET circuit is disabled and counting will not start until after a positive MASTER RESET pulse is applied and returns to a low level. The AUTO RESET consumes an appreciable amount of power and should not be used if low-power operation is desired. For reliable automatic power-on reset, V_DD should be greater than 5V.

The RC oscillator, shown in Figure 2, oscillates with a frequency determined by the RC network and is calculated using:

Where f is between 1kHz and 100kHz and R_S and 2R_TC.

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	Tipo	Título	Fecha
*	Data sheet	CD4541B datasheet (Rev. E)	21 ago 2003
	Selection guide	Logic Guide (Rev. AB)	12 jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 dic 2015
	User guide	LOGIC Pocket Data Book (Rev. B)	16 ene 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 jul 2004
	User guide	Signal Switch Data Book (Rev. A)	14 nov 2003
	Application note	Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics	03 dic 2001

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Encapsulado	Pines	Símbolos CAD, huellas y modelos 3D
PDIP (N)	14	Ultra Librarian
SOIC (D)	14	Ultra Librarian
SOP (NS)	14	Ultra Librarian
TSSOP (PW)	14	Ultra Librarian

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CD4541B

Temporizador programable CMOS - Tipo de alta tensión (20 V nominales)

CD4541B

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