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CD54HCT4046A

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Bucle de fase bloqueado con VCO CMOS logic de alta velocidad

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CD54HCT4046A

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Detalles del producto

Technology family HCT Bits (#) 1 Rating Military Operating temperature range (°C) -55 to 125
Technology family HCT Bits (#) 1 Rating Military Operating temperature range (°C) -55 to 125
CDIP (J) 16 135.3552 mm² 19.56 x 6.92
  • Operating Frequency Range
    • Up to 18MHz (Typ) at VCC = 5V
    • Minimum Center Frequency of 12MHz at VCC = 4.5V
  • Choice of Three Phase Comparators
    • EXCLUSIVE-OR
    • Edge-Triggered JK Flip-Flop
    • Edge-Triggered RS Flip-Flop
  • Excellent VCO Frequency Linearity
  • VCO-Inhibit Control for ON/OFF Keying and for Low Standby Power Consumption
  • Minimal Frequency Drift
  • Operating Power Supply Voltage Range
    • VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V
    • Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . -55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
  • Applications
    • FM Modulation and Demodulation
    • Frequency Synthesis and Multiplication
    • Frequency Discrimination
    • Tone Decoding
    • Data Synchronization and Conditioning
    • Voltage-to-Frequency Conversion
    • Motor-Speed Control
  • Operating Frequency Range
    • Up to 18MHz (Typ) at VCC = 5V
    • Minimum Center Frequency of 12MHz at VCC = 4.5V
  • Choice of Three Phase Comparators
    • EXCLUSIVE-OR
    • Edge-Triggered JK Flip-Flop
    • Edge-Triggered RS Flip-Flop
  • Excellent VCO Frequency Linearity
  • VCO-Inhibit Control for ON/OFF Keying and for Low Standby Power Consumption
  • Minimal Frequency Drift
  • Operating Power Supply Voltage Range
    • VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V
    • Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . -55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
  • Applications
    • FM Modulation and Demodulation
    • Frequency Synthesis and Multiplication
    • Frequency Discrimination
    • Tone Decoding
    • Data Synchronization and Conditioning
    • Voltage-to-Frequency Conversion
    • Motor-Speed Control

The ’HC4046A and ’HCT4046A are high-speed silicon-gate CMOS devices that are pin compatible with the CD4046B of the "4000B" series. They are specified in compliance with JEDEC standard number 7.

The ’HC4046A and ’HCT4046A are phase-locked-loop circuits that contain a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2 and PC3). A signal input and a comparator input are common to each comparator.

The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques.

The ’HC4046A and ’HCT4046A are high-speed silicon-gate CMOS devices that are pin compatible with the CD4046B of the "4000B" series. They are specified in compliance with JEDEC standard number 7.

The ’HC4046A and ’HCT4046A are phase-locked-loop circuits that contain a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2 and PC3). A signal input and a comparator input are common to each comparator.

The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques.
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Documentación técnica

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Tipo Título Fecha
* Data sheet CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A datasheet (Rev. J) 21 nov 2003
* SMD CD54HCT4046A SMD 5962-88757 21 jun 2016
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 jul 2021
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
Application note Implementation of FSK Modulation and Demodulation using CD74HC4046A 25 nov 2013
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
User guide Signal Switch Data Book (Rev. A) 14 nov 2003
Application note CMOS Phase-Locked-Loop Applications (Rev. B) 19 sep 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 jun 1997
Application note Designing With Logic (Rev. C) 01 jun 1997
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 may 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 abr 1996

Diseño y desarrollo

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Encapsulado Pines Símbolos CAD, huellas y modelos 3D
CDIP (J) 16 Ultra Librarian
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  • Monitoreo continuo de confiabilidad
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