CD74HC4017

Name: CD74HC4017
Brand: TI
SKU: CD74HC4017
Price: 0.231 USD

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Contador/divisor de décadas CMOS Logic de alta velocidad con 10 salidas decodificadas

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Hoja de datos

document-pdfAcrobat CD54HC4017/CD74HC4017 High-Speed CMOS Logic Decade Counter/Divider datasheet (Rev. D) (Inglés)

CD74HC4017

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Detalles del producto

Function

Counter

Bits (#)

10

Technology family

HC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Standard CMOS

Output type

Push-Pull

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-55 to 125

Rating

Catalog

Function

Counter

Bits (#)

10

Technology family

HC

Supply voltage (min) (V)

2

Supply voltage (max) (V)

6

Input type

Standard CMOS

Output type

Push-Pull

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-55 to 125

Rating

Catalog

PDIP (N)

16

181.42 mm² 19.3 x 9.4

SOIC (D)

16

59.4 mm² 9.9 x 6

SOP (NS)

16

79.56 mm² 10.2 x 7.8

TSSOP (PW)

16

32 mm² 5 x 6.4

Fully Static Operation
Buffered Inputs
Common Reset
Positive Edge Clocking
Typical f_MAX = 50MHz at V_CC =5V,C_L = 15pF, T_A =25°C
Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55°C to 125°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V

Fully Static Operation
Buffered Inputs
Common Reset
Positive Edge Clocking
Typical f_MAX = 50MHz at V_CC =5V,C_L = 15pF, T_A =25°C
Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55°C to 125°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V

The ’HC4017 is a high speed silicon gate CMOS 5-stage Johnson counter with 10 decoded outputs. Each of the decoded outputs is normally low and sequentially goes high on the low to high transition clock period of the 10 clock period cycle. The CARRY (TC) output transitions low to high after OUTPUT 10 goes low, and can be used in conjunction with the CLOCK ENABLE (CE\) to cascade several stages. The CLOCK ENABLE input disables counting when in the high state. A RESET (MR) input is also provided which when taken high sets all the decoded outputs, except "0", low.

The device can drive up to 10 low power Schottky equivalent loads.

The ’HC4017 is a high speed silicon gate CMOS 5-stage Johnson counter with 10 decoded outputs. Each of the decoded outputs is normally low and sequentially goes high on the low to high transition clock period of the 10 clock period cycle. The CARRY (TC) output transitions low to high after OUTPUT 10 goes low, and can be used in conjunction with the CLOCK ENABLE (CE\) to cascade several stages. The CLOCK ENABLE input disables counting when in the high state. A RESET (MR) input is also provided which when taken high sets all the decoded outputs, except "0", low.

The device can drive up to 10 low power Schottky equivalent loads.

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Contador de décadas CMOS con 10 salidas decodificadas Voltage range (3V to 18V), average propagation delay (130ns)

Documentación técnica

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	Tipo	Título	Fecha
*	Data sheet	CD54HC4017/CD74HC4017 High-Speed CMOS Logic Decade Counter/Divider datasheet (Rev. D)	16 oct 2003
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)	26 jul 2021
	Selection guide	Logic Guide (Rev. AB)	12 jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 dic 2015
	User guide	LOGIC Pocket Data Book (Rev. B)	16 ene 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 jul 2004
	User guide	Signal Switch Data Book (Rev. A)	14 nov 2003
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	29 ago 2002
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)	01 jun 1997
	Application note	Designing With Logic (Rev. C)	01 jun 1997
	Application note	Input and Output Characteristics of Digital Integrated Circuits	01 oct 1996
	Application note	Live Insertion	01 oct 1996
	Application note	SN54/74HCT CMOS Logic Family Applications and Restrictions	01 may 1996
	Application note	Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc	01 abr 1996

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

El módulo de evaluación (EVM) 14-24-LOGIC-EVM está diseñado para admitir cualquier dispositivo lógico que esté en un empaquetado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.

Guía del usuario: PDF | HTML

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This reference design demonstrates an efficient, low-noise five-rail power supply design for very high-speed Data Acquisition (DAQ) systems capable of > 12.8 GSPS. The power supply DC/DC converters are frequency-synchronized and phase-shifted in order to minimize input current ripple and (...)

Design guide: PDF

Esquema: PDF

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TIDA-00744 — Diseño de referencia de potencia de nivel de sistema de 50 W para sistemas de infoentretenimiento de

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The design has protections, such as load dump through TVS (ISO pulse testing), as well as reverse voltage (innovative smart diode with very low Iq) protection. Furthermore, all the controllers (boost and (...)

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Diseños de referencia

PMP10749 — Diseño de referencia de potencia a nivel de sistema de 100 W para un sistema de infoentretenimiento

PMP10749 is a 100-W system-level SMPS design for a higher-power automotive infotainment system. The design has protections, such as load dump through TVS (ISO pulse testing), as well as reverse voltage (innovative smart diode with very low Iq) protection. Furthermore, all the controllers (boost and (...)

Test report: PDF

Esquema: PDF

Encapsulado	Pines	Símbolos CAD, huellas y modelos 3D
PDIP (N)	16	Ultra Librarian
SOIC (D)	16	Ultra Librarian
SOP (NS)	16	Ultra Librarian
TSSOP (PW)	16	Ultra Librarian

Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

CD74HC4017

Contador/divisor de décadas CMOS Logic de alta velocidad con 10 salidas decodificadas

CD74HC4017

Detalles del producto

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Documentación técnica

Diseño y desarrollo

14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

TIDA-01027 — Diseño de referencia de fuente de alimentación de bajo ruido, que maximiza el rendimiento en sistema

TIDA-00744 — Diseño de referencia de potencia de nivel de sistema de 50 W para sistemas de infoentretenimiento de

PMP10749 — Diseño de referencia de potencia a nivel de sistema de 100 W para un sistema de infoentretenimiento

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