Inicio Lógica y traducción de voltaje Traductores de tensión y desplazadores de nivel Traductores de tensión de dirección fija
Inicio
Lógica y traducción de voltaje
Traductores de tensión y desplazadores de nivel
Traductores de tensión de dirección fija

SN74AUP1T17

ACTIVO

Puerta de búfer de disparador Schmitt única de baja potencia, salida CMOS de 3.3 V, entrada de 1.8 V

Haga su pedido ahora
Hoja de datos

SN74AUP1T17

ACTIVO
Hoja de datos Haga su pedido ahora

Detalles del producto

Technology family AUP1T Bits (#) 1 Configuration 1 Ch A to B 0 Ch B to A High input voltage (min) (V) 1.35 High input voltage (max) (V) 3.6 Vout (min) (V) 0 Vout (max) (V) 3.6 Data rate (max) (Mbps) 200 IOH (max) (mA) -4 IOL (max) (mA) -4 Supply current (max) (µA) 3.6 Features 4.2 Input type Schmitt-Trigger Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AUP1T Bits (#) 1 Configuration 1 Ch A to B 0 Ch B to A High input voltage (min) (V) 1.35 High input voltage (max) (V) 3.6 Vout (min) (V) 0 Vout (max) (V) 3.6 Data rate (max) (Mbps) 200 IOH (max) (mA) -4 IOL (max) (mA) -4 Supply current (max) (µA) 3.6 Features 4.2 Input type Schmitt-Trigger Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
SOT-SC70 (DCK) 5 4.2 mm² 2 x 2.1
  • Single-Supply Voltage Translator
  • Output Level Up to Supply VCC CMOS Level
    • 1.8 V to 3.3 V (at VCC = 3.3 V)
    • 2.5 V to 3.3 V (at VCC = 3.3 V)
    • 1.8 V to 2.5 V (at VCC = 2.5 V)
    • 3.3 V to 2.5 V (at VCC = 2.5 V
  • Schmitt-Trigger Inputs Reject Input Noise and
    Provide Better Output Signal Integrity
  • Ioff Supports Partial Power Down (VCC = 0 V)
  • Very Low Static Power Consumption:
    0.1 µA
  • Very Low Dynamic Power Consumption:
    0.9 µA
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • Pb-Free Packages Available: SC-70 (DCK)

    2 × 2.1 × 0.65 mm (Height 1.1 mm)
  • More Gate Options Available at
    www.ti.com/littlelogic
  • ESD Performance Tested Per JESD 22
    • 2000-V Human Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • APPLICATIONS
    • AV Receivers
    • Audio Dock: Portable
    • Blu-ray Players and Home Theaters
    • MP3 Players and Recorders
    • Personal Digital Assistant (PDA)
    • Power: Telecom/Server AC/DC Supply: Single
      Controller: Analog and Digital
    • Solid State Drive (SSD): Client and Enterprise
    • TV: LCD/Digital and High-Definition (HDTV)
    • Tablet: Enterprise
    • Video Analytics: Servers
    • Wireless Headsets, Keyboards, and Mice

All other trademarks are the property of their respective owners
  • Single-Supply Voltage Translator
  • Output Level Up to Supply VCC CMOS Level
    • 1.8 V to 3.3 V (at VCC = 3.3 V)
    • 2.5 V to 3.3 V (at VCC = 3.3 V)
    • 1.8 V to 2.5 V (at VCC = 2.5 V)
    • 3.3 V to 2.5 V (at VCC = 2.5 V
  • Schmitt-Trigger Inputs Reject Input Noise and
    Provide Better Output Signal Integrity
  • Ioff Supports Partial Power Down (VCC = 0 V)
  • Very Low Static Power Consumption:
    0.1 µA
  • Very Low Dynamic Power Consumption:
    0.9 µA
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • Pb-Free Packages Available: SC-70 (DCK)

    2 × 2.1 × 0.65 mm (Height 1.1 mm)
  • More Gate Options Available at
    www.ti.com/littlelogic
  • ESD Performance Tested Per JESD 22
    • 2000-V Human Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • APPLICATIONS
    • AV Receivers
    • Audio Dock: Portable
    • Blu-ray Players and Home Theaters
    • MP3 Players and Recorders
    • Personal Digital Assistant (PDA)
    • Power: Telecom/Server AC/DC Supply: Single
      Controller: Analog and Digital
    • Solid State Drive (SSD): Client and Enterprise
    • TV: LCD/Digital and High-Definition (HDTV)
    • Tablet: Enterprise
    • Video Analytics: Servers
    • Wireless Headsets, Keyboards, and Mice

All other trademarks are the property of their respective owners

The SN74AUP1T17 performs the Boolean function Y = A with designation for logic-level translation applications with output referenced to supply VCC.

AUP technology is the industry–s lowest-power logic technology designed for use in extending battery-life in operating. All input levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCC supply. This product also maintains excellent signal integrity.

The wide VCC range of 2.3 V to 3.6 V allows the possibility of switching output level to connect to external controllers or processors.

Schmitt-trigger inputs (ΔVT = 210 mV between positive and negative input transitions) offer improved noise immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition.

Ioff is a feature that allows for powered-down conditions (VCC = 0 V) and is important in portable and mobile applications. When VCC = 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of the device. No damage occurs to the device under these conditions.

The SN74AUP1T17 is designed with optimized current-drive capability of 4 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.

The SN74AUP1T17 performs the Boolean function Y = A with designation for logic-level translation applications with output referenced to supply VCC.

AUP technology is the industry–s lowest-power logic technology designed for use in extending battery-life in operating. All input levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCC supply. This product also maintains excellent signal integrity.

The wide VCC range of 2.3 V to 3.6 V allows the possibility of switching output level to connect to external controllers or processors.

Schmitt-trigger inputs (ΔVT = 210 mV between positive and negative input transitions) offer improved noise immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition.

Ioff is a feature that allows for powered-down conditions (VCC = 0 V) and is important in portable and mobile applications. When VCC = 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of the device. No damage occurs to the device under these conditions.

The SN74AUP1T17 is designed with optimized current-drive capability of 4 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.
filter Buscar otro/a Traductores de tensión de dirección fija
Descargar Ver vídeo con transcripción Video

Documentación técnica

star =Principal documentación para este producto seleccionada por TI
No se encontraron resultados. Borre su búsqueda y vuelva a intentarlo.
Ver todo 6
Tipo Título Fecha
* Data sheet SN74AUP1T17 Low Power, 1.8/2.5/3.3-V Input, 3.3-V CMOS Output, Single Schmitt-Trigger Buffer Gate datasheet (Rev. A) PDF | HTML 30 jun 2015
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 02 oct 2024
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 12 jul 2024
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 03 jul 2024
Selection guide Voltage Translation Buying Guide (Rev. A) 15 abr 2021
Application brief Understanding Schmitt Triggers (Rev. A) PDF | HTML 22 may 2019

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

5-8-LOGIC-EVM — Módulo de evaluación lógica genérico para encapsulados DCK, DCT, DCU, DRL y DBV de 5 a 8 pines

Módulo de evaluación (EVM) flexible diseñado para admitir cualquier dispositivo que tenga un encapsulado DCK, DCT, DCU, DRL o DBV en un recuento de 5 a 8 pines.
Guía del usuario: PDF
No disponible en TI.com
Diseños de referencia

TIDA-00268 — Diseño de referencia de periféricos de un solo puerto Thunderbolt™

The TI Thunderbolt™ Single Port Peripheral reference design is optimized for Thunderbolt 2 systems which have a bandwidth of 20Gbps. The design utilizes the TPS65980 power management unit to reduce the BOM cost up to 50% and reduce the area about 40% over a discrete implementation. This (...)
Design guide: PDF
Esquema: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
SOT-SC70 (DCK) 5 Ultra Librarian
Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

Ver todos los temas del foro en inglés

El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.

Si tiene preguntas sobre la calidad, el paquete o el pedido de productos de TI, consulte el soporte de TI. ​​​​​​​​​​​​​​

Videos