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SN74AUP3G04

ACTIVO

Inversores de baja potencia de 3 canales, 0.8 V a 3.6 V

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SN74AUP3G04

ACTIVO
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Detalles del producto

Technology family AUP Supply voltage (min) (V) 0.8 Supply voltage (max) (V) 3.6 Number of channels 3 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 0.9 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AUP Supply voltage (min) (V) 0.8 Supply voltage (max) (V) 3.6 Number of channels 3 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 0.9 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
DSBGA (YFP) 8 1.8 mm² 1 x 1.8 UQFN (RSE) 8 2.25 mm² 1.5 x 1.5 VSSOP (DCU) 8 6.2 mm² 2 x 3.1 X2SON (DQE) 8 1.4 mm² 1.4 x 1
  • Available in the Texas Instruments NanoStar Package
  • Low Static-Power Consumption
    (ICC = 0.9 µA Maximum)
  • Low Dynamic-Power Consumption
    (Cpd = 4.3 pF Typ at 3.3 V)
  • Low Input Capacitance (Ci = 1.5 pF Typical)
  • Low Noise – Overshoot and Undershoot
    <10% of VCC
  • Ioff Supports Live Insertion, Partial PowerDown Mode,
    and Back Drive Protection
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4.3 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)

NanoStar Is a trademark of Texas Instruments
  • Available in the Texas Instruments NanoStar Package
  • Low Static-Power Consumption
    (ICC = 0.9 µA Maximum)
  • Low Dynamic-Power Consumption
    (Cpd = 4.3 pF Typ at 3.3 V)
  • Low Input Capacitance (Ci = 1.5 pF Typical)
  • Low Noise – Overshoot and Undershoot
    <10% of VCC
  • Ioff Supports Live Insertion, Partial PowerDown Mode,
    and Back Drive Protection
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4.3 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)

NanoStar Is a trademark of Texas Instruments

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).

The SN74AUP3G04 performs the Boolean function Y = A in positive logic.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).

The SN74AUP3G04 performs the Boolean function Y = A in positive logic.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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Documentación técnica

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Tipo Título Fecha
* Data sheet SN74AUP3G04 Low-Power Triple Inverter Gate datasheet (Rev. C) 21 abr 2011
Application brief Understanding Schmitt Triggers (Rev. A) PDF | HTML 22 may 2019
Selection guide Little Logic Guide 2018 (Rev. G) 06 jul 2018
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note How to Select Little Logic (Rev. A) 26 jul 2016
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

5-8-LOGIC-EVM — Módulo de evaluación lógica genérico para encapsulados DCK, DCT, DCU, DRL y DBV de 5 a 8 pines

Módulo de evaluación (EVM) flexible diseñado para admitir cualquier dispositivo que tenga un encapsulado DCK, DCT, DCU, DRL o DBV en un recuento de 5 a 8 pines.
Guía del usuario: PDF
No disponible en TI.com
Modelo de simulación

SN74AUP3G04 Behavioral SPICE Model

SCEM668.ZIP (7 KB) - PSpice Model
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Encapsulado Pines Símbolos CAD, huellas y modelos 3D
DSBGA (YFP) 8 Ultra Librarian
UQFN (RSE) 8 Ultra Librarian
VSSOP (DCU) 8 Ultra Librarian
X2SON (DQE) 8 Ultra Librarian
Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

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