These d-c triggered multivibrators feature output pulse-duration control by three methods. The basic pulse time is programmed by selection of external resistance and capacitance values (see typical application data). The '122 and 'LS122 have internal timing resistors that allow the circuits to be used with only an external capacitor, if so desired. Once triggered, the basic pulse duration may be extended by retriggering the gated low-level-active (A) or high-level-active (B) inputs, or be reduced by use of the overriding clear. Figure 1 illustrates pulse control by retriggering and early clear.
The 'LS122 and 'LS123 are provided enough Schmitt hysteresis to ensure jitter-free triggering from the B input with transition rates as slow as 0.1 millivolt per nanosecond.
The Rint is nominally 10 k
for '122 and 'LS122.
| Tipo | Título | Fecha | ||
|---|---|---|---|---|
| * | Data sheet | Retriggerable Monostable Multivibrators datasheet | 01 dic 1983 | |
| Application note | Designing With the SN74LVC1G123 Monostable Multivibrator (Rev. A) | PDF | HTML | 13 mar 2020 | |
| Selection guide | Logic Guide (Rev. AB) | 12 jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 dic 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 ene 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 jul 2004 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 ago 2002 | ||
| Application note | Designing With Logic (Rev. C) | 01 jun 1997 | ||
| Application note | Designing with the SN54/74LS123 (Rev. A) | 01 mar 1997 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 01 oct 1996 | ||
| Application note | Live Insertion | 01 oct 1996 |
Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.
El módulo de evaluación 14-24-LOGIC-EVM (EVM) está diseñado para admitir cualquier dispositivo lógico que esté en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.
| Encapsulado | Pines | Símbolos CAD, huellas y modelos 3D |
|---|---|---|
| PDIP (N) | 14 | Ultra Librarian |
| SOIC (D) | 14 | Ultra Librarian |
| SOP (NS) | 14 | Ultra Librarian |
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