The SN54165 and SN74165 devices are obsolete and are no longer supplied.
The ’165 and ’LS165A are 8-bit serial shift registers that shift the data in the direction of QA toward QH when clocked. Parallel-in access to each stage is made available by eight individual, direct data inputs that are enabled by a low level at the shift/load (SH/LD\) input. These registers also feature gated clock (CLK) inputs and complementary outputs from the eighth bit. All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design.
Clocking is accomplished through a two-input positive-NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with SH/LD\ high enables the other clock input. Clock inhibit (CLK INH) should be changed to the high level only while CLK is high. Parallel loading is inhibited as long as SH/LD\ is high. Data at the parallel inputs are loaded directly into the register while SH/LD\ is low, independently of the levels of CLK, CLK INH, or serial (SER) inputs.
| Tipo | Título | Fecha | ||
|---|---|---|---|---|
| * | Data sheet | Parallel-Load 8-Bit Shift Registers datasheet (Rev. D) | 12 feb 2002 | |
| Application note | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 15 dic 2022 | |
| Selection guide | Logic Guide (Rev. AB) | 12 jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 dic 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 ene 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 jul 2004 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 ago 2002 | ||
| Application note | Designing With Logic (Rev. C) | 01 jun 1997 | ||
| Application note | Designing with the SN54/74LS123 (Rev. A) | 01 mar 1997 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 01 oct 1996 | ||
| Application note | Live Insertion | 01 oct 1996 |
Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.
El módulo de evaluación (EVM) 14-24-LOGIC-EVM está diseñado para admitir cualquier dispositivo lógico que esté en un empaquetado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.
| Encapsulado | Pines | Símbolos CAD, huellas y modelos 3D |
|---|---|---|
| PDIP (N) | 16 | Ultra Librarian |
| SOIC (D) | 16 | Ultra Librarian |
| SOP (NS) | 16 | Ultra Librarian |
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