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SN74LVC1G125-Q1

ACTIVO

Búfer único de 1.65 V a 5.5 V, con salidas de 3 estados de calidad automotriz

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SN74LVC1G125-Q1

ACTIVO
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Detalles del producto

Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 1 IOL (max) (mA) 32 Supply current (max) (µA) 10 IOH (max) (mA) -32 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Automotive Operating temperature range (°C) -40 to 125
Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 1 IOL (max) (mA) 32 Supply current (max) (µA) 10 IOH (max) (mA) -32 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Automotive Operating temperature range (°C) -40 to 125
SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8 SOT-SC70 (DCK) 5 4.2 mm² 2 x 2.1 USON (DRY) 6 1.45 mm² 1.45 x 1
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature Range
    • Device Human-Body Model (HBM) ESD Classification Level 2
    • Device Charged-Device Model (CDM) ESD Classification Level C5
  • Available in the small 1.45-mm2 package (DRY) With 0.5-mm Pitch
  • Supports 5-V VCC Operation
  • Over-voltage tolerant inputs accept voltages to 5.5 V
  • Provides down translation to VCC
  • Max tpd of 3.7 ns at 3.3 V
  • Low power consumption, 10-µA Max ICC
  • ±24-mA Output drive at 3.3 V
  • Ioff supports live insertion, partial-power-down mode, and back-drive protection
  • Latch-up performance exceeds 100 mA Per JESD 78, Class II
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature Range
    • Device Human-Body Model (HBM) ESD Classification Level 2
    • Device Charged-Device Model (CDM) ESD Classification Level C5
  • Available in the small 1.45-mm2 package (DRY) With 0.5-mm Pitch
  • Supports 5-V VCC Operation
  • Over-voltage tolerant inputs accept voltages to 5.5 V
  • Provides down translation to VCC
  • Max tpd of 3.7 ns at 3.3 V
  • Low power consumption, 10-µA Max ICC
  • ±24-mA Output drive at 3.3 V
  • Ioff supports live insertion, partial-power-down mode, and back-drive protection
  • Latch-up performance exceeds 100 mA Per JESD 78, Class II

This bus buffer gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G125-Q1 device is a single line driver with a 3-state output. The output is disabled when the output-enable ( OE) input is high.

The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.

The SN74LVC1G125-Q1 device is available in a variety of packages including the small DRY package with a body size of 1.45 mm × 1.00 mm.

This bus buffer gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G125-Q1 device is a single line driver with a 3-state output. The output is disabled when the output-enable ( OE) input is high.

The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.

The SN74LVC1G125-Q1 device is available in a variety of packages including the small DRY package with a body size of 1.45 mm × 1.00 mm.
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Documentación técnica

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* Data sheet SN74LVC1G125-Q1 Single-BUS buffer gate with 3-state output datasheet (Rev. E) PDF | HTML 12 ago 2020
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 jul 2021
Application note Optimizing On-Board and Wireless Charger Systems Using Logic and Translation (Rev. A) PDF | HTML 01 abr 2021
Application note Drive Transmission Lines With Logic PDF | HTML 20 oct 2020
Selection guide Little Logic Guide 2018 (Rev. G) 06 jul 2018
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note How to Select Little Logic (Rev. A) 26 jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
More literature Automotive Logic Devices Brochure 27 ago 2014
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 jun 2004
User guide Signal Switch Data Book (Rev. A) 14 nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 nov 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 dic 2002
Application note Texas Instruments Little Logic Application Report 01 nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 may 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 may 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 mar 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 dic 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 ago 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 jun 1997
Application note LVC Characterization Information 01 dic 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 oct 1996
Application note Live Insertion 01 oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 may 1996

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

5-8-LOGIC-EVM — Módulo de evaluación lógica genérico para encapsulados DCK, DCT, DCU, DRL y DBV de 5 a 8 pines

Módulo de evaluación (EVM) flexible diseñado para admitir cualquier dispositivo que tenga un encapsulado DCK, DCT, DCU, DRL o DBV en un recuento de 5 a 8 pines.
Guía del usuario: PDF
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Modelo de simulación

SN74LVC1G125 Behavioral SPICE Model

SCEM639.ZIP (7 KB) - PSpice Model
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Design guide: PDF
Esquema: PDF
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Design guide: PDF
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Diseños de referencia

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This camera hub reference design allows connection of up to four 1.3-megapixel cameras to a TDA3x system-on-chip (SoC) evaluation module (EVM). Each camera connects to the hub through a single coax cable. Using FPD-Link III connections, the cameras are connected to a four-port deserializer. The (...)
Design guide: PDF
Esquema: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
SOT-23 (DBV) 5 Ultra Librarian
SOT-SC70 (DCK) 5 Ultra Librarian
USON (DRY) 6 Ultra Librarian
Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

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