Inicio Lógica y traducción de voltaje Circuitos integrados lógicos configurables y programables Configurable gates
Inicio
Lógica y traducción de voltaje
Circuitos integrados lógicos configurables y programables
Configurable gates

SN74LVC1G3208-Q1

ACTIVO

Puerta OR-AND única positiva de 3 entradas en catálogo automotriz

Haga su pedido ahora
Hoja de datos

SN74LVC1G3208-Q1

ACTIVO
Hoja de datos Haga su pedido ahora

Detalles del producto

Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 1 Inputs per channel 3 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Automotive Operating temperature range (°C) -40 to 85
Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 1 Inputs per channel 3 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Automotive Operating temperature range (°C) -40 to 85
SOT-SC70 (DCK) 6 4.2 mm² 2 x 2.1
  • Qualified for Automotive Applications
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 5 ns at 3.3 V
  • Low Power Consumption, 10-μA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input
    (Vhys = 250 mV Typ at 3.3 V)
  • Can Be Used in Three Combinations:
    • OR-AND Gate
    • OR Gate
    • AND Gate
  • Ioff Supports Partial-Power-Down Mode Operation
  • Qualified for Automotive Applications
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 5 ns at 3.3 V
  • Low Power Consumption, 10-μA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input
    (Vhys = 250 mV Typ at 3.3 V)
  • Can Be Used in Three Combinations:
    • OR-AND Gate
    • OR Gate
    • AND Gate
  • Ioff Supports Partial-Power-Down Mode Operation

This device is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G3208-Q1 is a single 3-input positive OR-AND gate. It performs the Boolean function Y = (A + B) ⋅ C in positive logic.

By tying one input to GND or VCC, the SN74LVC1G3208-Q1 offers two more functions. When C is tied to VCC, this device performs as a 2-input OR gate (Y = A + B). When A is tied to GND, the device works as a 2-input AND gate (Y = B ⋅ C). This device also works as a 2-input AND gate when B is tied to GND (Y = A ⋅ C).

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This device is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G3208-Q1 is a single 3-input positive OR-AND gate. It performs the Boolean function Y = (A + B) ⋅ C in positive logic.

By tying one input to GND or VCC, the SN74LVC1G3208-Q1 offers two more functions. When C is tied to VCC, this device performs as a 2-input OR gate (Y = A + B). When A is tied to GND, the device works as a 2-input AND gate (Y = B ⋅ C). This device also works as a 2-input AND gate when B is tied to GND (Y = A ⋅ C).

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
filter Buscar otro/a Configurable gates
Descargar Ver vídeo con transcripción Video

Documentación técnica

star =Principal documentación para este producto seleccionada por TI
No se encontraron resultados. Borre su búsqueda y vuelva a intentarlo.
Ver todo 27
Tipo Título Fecha
* Data sheet Single 3-Input Positive OR-AND Gate datasheet 29 dic 2010
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 jul 2018
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note How to Select Little Logic (Rev. A) 26 jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 jun 2004
User guide Signal Switch Data Book (Rev. A) 14 nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 nov 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 dic 2002
Application note Texas Instruments Little Logic Application Report 01 nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 may 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 may 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 mar 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 dic 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 ago 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 jun 1997
Application note LVC Characterization Information 01 dic 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 oct 1996
Application note Live Insertion 01 oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 may 1996

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

5-8-LOGIC-EVM — Módulo de evaluación lógica genérico para encapsulados DCK, DCT, DCU, DRL y DBV de 5 a 8 pines

Módulo de evaluación (EVM) flexible diseñado para admitir cualquier dispositivo que tenga un encapsulado DCK, DCT, DCU, DRL o DBV en un recuento de 5 a 8 pines.
Guía del usuario: PDF
No disponible en TI.com
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
SOT-SC70 (DCK) 6 Ultra Librarian
Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

Ver todos los temas del foro en inglés

El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.

Si tiene preguntas sobre la calidad, el paquete o el pedido de productos de TI, consulte el soporte de TI. ​​​​​​​​​​​​​​

Videos