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Compuertas lógicas
Compuertas NAND

SN74LVC2G00

ACTIVO

Puertas NAND de 2 canales, 2 entradas, 1.65 V a 5.5 V

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SN74LVC2G00

ACTIVO
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Detalles del producto

Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 2 Inputs per channel 2 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 2 Inputs per channel 2 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
DSBGA (YZP) 8 2.8125 mm² 2.25 x 1.25 SSOP (DCT) 8 11.8 mm² 2.95 x 4 VSSOP (DCU) 8 6.2 mm² 2 x 3.1
  • Available in the Texas Instruments
    NanoFree™ Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.3 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA =
    25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial Power
    Down Mode, and Back Drive Protection
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model
    • 1000-V Charged-Device Model
  • Available in the Texas Instruments
    NanoFree™ Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.3 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA =
    25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial Power
    Down Mode, and Back Drive Protection
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model
    • 1000-V Charged-Device Model

This dual 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G00 device performs the Boolean function Y = A × B or Y = A + B in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This dual 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G00 device performs the Boolean function Y = A × B or Y = A + B in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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SN74AUP2G00 ACTIVO Puertas NAND de baja potencia de 2 canales, 2 entradas, de 0.8 V a 3.6 V Smaller voltage range (0.8V to 3.6V), longer average propagation delay (8ns), lower average drive strength (4mA)

Documentación técnica

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Tipo Título Fecha
* Data sheet SN74LVC2G00 Dual 2-Input Positive-NAND Gate datasheet (Rev. N) PDF | HTML 12 ene 2015
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 jul 2018
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note How to Select Little Logic (Rev. A) 26 jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 jun 2004
User guide Signal Switch Data Book (Rev. A) 14 nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 nov 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 dic 2002
Application note Texas Instruments Little Logic Application Report 01 nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 may 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 may 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 mar 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 dic 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 ago 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 jun 1997
Application note LVC Characterization Information 01 dic 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 oct 1996
Application note Live Insertion 01 oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 may 1996

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

5-8-LOGIC-EVM — Módulo de evaluación lógica genérico para encapsulados DCK, DCT, DCU, DRL y DBV de 5 a 8 pines

Módulo de evaluación (EVM) flexible diseñado para admitir cualquier dispositivo que tenga un encapsulado DCK, DCT, DCU, DRL o DBV en un recuento de 5 a 8 pines.
Guía del usuario: PDF
No disponible en TI.com
Modelo de simulación

SN74LVC2G00 Behavioral SPICE Model

SCEM625.ZIP (7 KB) - PSpice Model
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Modelo de simulación

SN74LVC2G00 IBIS Model (Rev. A)

SCEM251A.ZIP (45 KB) - IBIS Model
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Design guide: PDF
Esquema: PDF
Diseños de referencia

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This verified design outlines a hardware pace detection solution for ECG using slope detection. The circuit is designed to work smoothly with the ADS1298 through the PACEOUT pins from the ADC directly feeding the input of the pace detection circuit. When a pace signal is detected, the output from (...)
Guía del usuario: PDF
Esquema: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
DSBGA (YZP) 8 Ultra Librarian
SSOP (DCT) 8 Ultra Librarian
VSSOP (DCU) 8 Ultra Librarian
Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

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