SN74LVC2G240

Name: SN74LVC2G240
Brand: TI
SKU: SN74LVC2G240
Price: 0.205 USD

ACTIVO

Inversores de 2 canales, 1.65 V a 5.5 V con salidas de 3 estados

Haga su pedido ahora

Hoja de datos

document-pdfAcrobat Dual Buffer/Driver With 3-State Outputs, SN74LVC2G240 datasheet (Rev. I) (Inglés)

SN74LVC2G240

ACTIVO

Hoja de datos

Haga su pedido ahora

Detalles del producto

Technology family

LVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

5.5

Number of channels

2

IOL (max) (mA)

32

IOH (max) (mA)

-32

Supply current (max) (µA)

10

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Technology family

LVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

5.5

Number of channels

2

IOL (max) (mA)

32

IOH (max) (mA)

-32

Supply current (max) (µA)

10

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

DSBGA (YZP)

8

2.8125 mm² 2.25 x 1.25

SSOP (DCT)

8

11.8 mm² 2.95 x 4

VSSOP (DCU)

8

6.2 mm² 2 x 3.1

Available in the Texas Instruments NanoFree Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 4.6 ns at 3.3 V
Low Power Consumption, 10-µA Max I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Can Be Used as a Down Translator to Translate Inputs From a Max of 5.5 V Down to the V_CC Level
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 1000-V Charged-Device Model (C101)

Available in the Texas Instruments NanoFree Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 4.6 ns at 3.3 V
Low Power Consumption, 10-µA Max I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Can Be Used as a Down Translator to Translate Inputs From a Max of 5.5 V Down to the V_CC Level
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 1000-V Charged-Device Model (C101)

This dual buffer driver is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC2G240 device is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is organized as two 1-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A input to the Y output. When OE is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This dual buffer driver is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC2G240 device is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is organized as two 1-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A input to the Y output. When OE is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

filter

Buscar otro/a Búferes y controladores inversores

Descargar Ver vídeo con transcripción Video

Productos similares que pueden interesarle

open-in-new

Comparar alternativas

Pin por pin con la misma funcionalidad que el dispositivo comparado

SN74AUP2G04

ACTIVO

Inversores de baja potencia de 2 canales, 0.8 V a 3.6 V Smaller voltage range (0.8V to 3.6V), longer average propagation delay (8ns), lower average drive strength (4mA)

Documentación técnica

star

=Principal documentación para este producto seleccionada por TI

No se encontraron resultados. Borre su búsqueda y vuelva a intentarlo.

Ver todo 28

	Tipo	Título	Fecha
*	Data sheet	Dual Buffer/Driver With 3-State Outputs, SN74LVC2G240 datasheet (Rev. I)	25 nov 2013
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)	26 jul 2021
	Application brief	High-Performance 16-bit PWM to 4- to 20-mA DAC for Field Transmitters	26 mar 2020
	Selection guide	Little Logic Guide 2018 (Rev. G)	06 jul 2018
	Selection guide	Logic Guide (Rev. AB)	12 jun 2017
	Application note	How to Select Little Logic (Rev. A)	26 jul 2016
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 dic 2015
	User guide	LOGIC Pocket Data Book (Rev. B)	16 ene 2007
	Product overview	Design Summary for WCSP Little Logic (Rev. B)	04 nov 2004
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 jul 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)	22 jun 2004
	User guide	Signal Switch Data Book (Rev. A)	14 nov 2003
	Application note	Use of the CMOS Unbuffered Inverter in Oscillator Circuits	06 nov 2003
	User guide	LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)	18 dic 2002
	Application note	Texas Instruments Little Logic Application Report	01 nov 2002
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	29 ago 2002
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards	13 jun 2002
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)	22 may 2002
	Application note	Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices	10 may 2002
	More literature	STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS	27 mar 2002
	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices	01 dic 1997
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)	01 ago 1997
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)	01 jun 1997
	Application note	LVC Characterization Information	01 dic 1996
	Application note	Input and Output Characteristics of Digital Integrated Circuits	01 oct 1996
	Application note	Live Insertion	01 oct 1996
	Design guide	Low-Voltage Logic (LVC) Designer's Guide	01 sep 1996
	Application note	Understanding Advanced Bus-Interface Products Design Guide	01 may 1996

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

5-8-LOGIC-EVM — Módulo de evaluación lógica genérico para encapsulados DCK, DCT, DCU, DRL y DBV de 5 a 8 pines

Módulo de evaluación (EVM) flexible diseñado para admitir cualquier dispositivo que tenga un encapsulado DCK, DCT, DCU, DRL o DBV en un recuento de 5 a 8 pines.

Guía del usuario: PDF