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Microcontroladores (MCU) y procesadores
Procesadores digitales de señales (DSP)

TMS320DM641

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Procesador de señal digital de punto fijo de imágenes y video

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TMS320DM641

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Detalles del producto

DSP type 1 C64x DSP (max) (MHz) 500 CPU 32-/64-bit Operating system DSP/BIOS Ethernet MAC 10/100 Rating Catalog Operating temperature range (°C) to
DSP type 1 C64x DSP (max) (MHz) 500 CPU 32-/64-bit Operating system DSP/BIOS Ethernet MAC 10/100 Rating Catalog Operating temperature range (°C) to
OMFCBGA (ZNZ) 548 729 mm² 27 x 27
  • High-Performance Digital Media Processor (TMS320DM641/TMS320DM640)
    • 2.5-, 2-, 1.67-ns Instruction Cycle Time
    • 400-, 500-, 600-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 3200, 4000, 4800 MIPS
    • Fully Software-Compatible With C64x™
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2™ Increased Orthogonality
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • Endianess: Little Endian, Big Endian
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 1024M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
    • 8 Independent Transmit (TX) and 1 Receive (RX) Channel
  • Management Data Input/Output (MDIO)
  • Two Configurable Video Ports (DM641)
  • One Configurable Video Port (DM640)
    • Providing a Glueless I/F to Common Video Decoder and Encoder Devices
    • Supports Multiple Resolutions and Video Standards
  • VCXO Interpolated Control Port (VIC)
    • Supports Audio/Video Synchronization
  • Host-Port Interface (HPI) [16-Bit] (DM641)
  • Multichannel Audio Serial Port (McASP)
    • Four Serial Data Pins
    • Wide Variety of I2S and Similar Bit Stream Format
    • Integrated Digital Audio I/F Transmitter Supports S/PDIF, IEC60958-1, AES-3, CP-430 Formats
  • Inter-Integrated Circuit (I2C) Bus
  • Two Multichannel Buffered Serial Ports
  • Three 32-Bit General-Purpose Timers
  • Eight General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible
  • 548-Pin Ball Grid Array (BGA) Package (GDK and ZDK Suffixes), 0.8-mm Ball Pitch
  • 548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
  • 0.13-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V I/Os, 1.2-V Internal (-400, -500)
  • 3.3-V I/Os, 1.4-V Internal (-600)

C64x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000 and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
  • High-Performance Digital Media Processor (TMS320DM641/TMS320DM640)
    • 2.5-, 2-, 1.67-ns Instruction Cycle Time
    • 400-, 500-, 600-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 3200, 4000, 4800 MIPS
    • Fully Software-Compatible With C64x™
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2™ Increased Orthogonality
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • Endianess: Little Endian, Big Endian
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 1024M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
    • 8 Independent Transmit (TX) and 1 Receive (RX) Channel
  • Management Data Input/Output (MDIO)
  • Two Configurable Video Ports (DM641)
  • One Configurable Video Port (DM640)
    • Providing a Glueless I/F to Common Video Decoder and Encoder Devices
    • Supports Multiple Resolutions and Video Standards
  • VCXO Interpolated Control Port (VIC)
    • Supports Audio/Video Synchronization
  • Host-Port Interface (HPI) [16-Bit] (DM641)
  • Multichannel Audio Serial Port (McASP)
    • Four Serial Data Pins
    • Wide Variety of I2S and Similar Bit Stream Format
    • Integrated Digital Audio I/F Transmitter Supports S/PDIF, IEC60958-1, AES-3, CP-430 Formats
  • Inter-Integrated Circuit (I2C) Bus
  • Two Multichannel Buffered Serial Ports
  • Three 32-Bit General-Purpose Timers
  • Eight General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible
  • 548-Pin Ball Grid Array (BGA) Package (GDK and ZDK Suffixes), 0.8-mm Ball Pitch
  • 548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
  • 0.13-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V I/Os, 1.2-V Internal (-400, -500)
  • 3.3-V I/Os, 1.4-V Internal (-600)

C64x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000 and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.

The TMS320C64x™ DSPs (including the TMS320DM641 and TMS320DM640 devices) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320DM641 (DM641) and TMS320DM640 (DM640) devices are based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the DM641 device offers cost-effective solutions to high-performance DSP programming challenges.

With performance of up to 3200 million instructions per second (MIPS) at a clock rate of 400 MHz, the DM640 device offers cost-effective solutions to high-performance DSP programming challenges.

The DM641/DM640 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs)-with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI™ architecture. The DM641 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The DM640 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 1600 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 3200 MMACS. The DM641/DM640 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The DM641/DM640 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 1-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: two configurable video ports (DM641); one configurable video port (DM640); a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO interpolated control port (VIC); one 4-bit multichannel buffered audio serial port (McASP0); an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a 16-bit host-port interface (HPI16); a 8-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 32-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

The DM641 device has two single-channel 8-bit configurable video port peripherals (VP0 and VP1). The DM640 device has one single-channel 8-bit configurable video port peripheral (VP0). These video port peripherals provide a glueless interface to common video decoder and encoder devices. The DM641/DM640 video port peripherals support multiple resolutions and video standards (e. g., CCIR601 and ITU-).

These video port peripherals are configurable and can support either video capture and/or video display modes.

For more details on the Video Port peripherals, see the TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).

The McASP0 port supports one transmit and one receive clock zone, with four serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The DM641/DM640 has sufficient bandwidth to support all 4 serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.

In addition, the McASP0 transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.

McASP0 also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range.

The VCXO interpolated control (VIC) port provides digital-to-analog conversion with resolution from 9-bits to up to 16-bits. The output of the VIC is a single bit interpolated D/A output. For more details on the VIC port, see the TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).

The ethernet media access controller (EMAC) provides an efficient interface between the DM641/DM640 DSP core processor and the network. The DM641/DM640 EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The DM641/DM640 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception. For more details on the EMAC, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device without continuously performing costly MDIO accesses. For more details on the MDIO, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The I2C0 port on the TMS320DM641/DM640 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The DM641/DM640 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code

The TMS320C64x™ DSPs (including the TMS320DM641 and TMS320DM640 devices) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320DM641 (DM641) and TMS320DM640 (DM640) devices are based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the DM641 device offers cost-effective solutions to high-performance DSP programming challenges.

With performance of up to 3200 million instructions per second (MIPS) at a clock rate of 400 MHz, the DM640 device offers cost-effective solutions to high-performance DSP programming challenges.

The DM641/DM640 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs)-with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI™ architecture. The DM641 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The DM640 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 1600 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 3200 MMACS. The DM641/DM640 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The DM641/DM640 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 1-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: two configurable video ports (DM641); one configurable video port (DM640); a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO interpolated control port (VIC); one 4-bit multichannel buffered audio serial port (McASP0); an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a 16-bit host-port interface (HPI16); a 8-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 32-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

The DM641 device has two single-channel 8-bit configurable video port peripherals (VP0 and VP1). The DM640 device has one single-channel 8-bit configurable video port peripheral (VP0). These video port peripherals provide a glueless interface to common video decoder and encoder devices. The DM641/DM640 video port peripherals support multiple resolutions and video standards (e. g., CCIR601 and ITU-).

These video port peripherals are configurable and can support either video capture and/or video display modes.

For more details on the Video Port peripherals, see the TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).

The McASP0 port supports one transmit and one receive clock zone, with four serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The DM641/DM640 has sufficient bandwidth to support all 4 serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.

In addition, the McASP0 transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.

McASP0 also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range.

The VCXO interpolated control (VIC) port provides digital-to-analog conversion with resolution from 9-bits to up to 16-bits. The output of the VIC is a single bit interpolated D/A output. For more details on the VIC port, see the TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).

The ethernet media access controller (EMAC) provides an efficient interface between the DM641/DM640 DSP core processor and the network. The DM641/DM640 EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The DM641/DM640 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception. For more details on the EMAC, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device without continuously performing costly MDIO accesses. For more details on the MDIO, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The I2C0 port on the TMS320DM641/DM640 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The DM641/DM640 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code
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Documentación técnica

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Tipo Título Fecha
* Data sheet TMS320DM641/TMS320DM640 Video/Imaging Fixed-Point Digital Signal Processors datasheet (Rev. F) 12 oct 2010
* Errata TMS320DM641, TMS320DM640 DSPs Silicon Errata (Silicon Revisions 2.0,1.2,1.1,1.0) (Rev. G) 31 ago 2005
User guide Emulation and Trace Headers Technical Reference Manual (Rev. I) 09 ago 2012
Application note Introduction to TMS320C6000 DSP Optimization 06 oct 2011
User guide TMS320C64x DSP Video Port/ VCXO Interpolated Control (VIC) Port Reference Guide (Rev. G) 12 nov 2010
User guide TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) 30 jul 2010
User guide TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q) 02 jul 2009
User guide TMS320C6000 DSP Multi-channel Audio Serial Port (McASP) Reference Guide (Rev. J) 20 nov 2008
Application note TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E) 04 sep 2007
Application note Migrating from TMS320DM642/3/1/0 to the TMS320DM648/7 07 jun 2007
Application note Thermal Considerations for the DM64xx, DM64x, and C6000 Devices 20 may 2007
User guide TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E) 11 abr 2007
Product overview TMS320C6000 DSP TCP/IP Stack Software (Rev. C) 04 abr 2007
User guide TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (Rev. D) 26 mar 2007
User guide TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (Rev. G) 14 dic 2006
User guide TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (Rev. C) 15 nov 2006
User guide TMS320C64x DSP Two-Level Internal Memory Reference Guide (Rev. C) 28 feb 2006
User guide TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide (Rev. C) 01 ene 2006
Application note TMS320DM640/1 Hardware Designer's Resource Guide (Rev. A) 24 oct 2005
Application note Migrating from TMS320C64x to TMS320C64x+ (Rev. A) 20 oct 2005
Product overview TMS320DM64x Digital Media Processors - Product Bulletin (Rev. C) 30 ago 2005
User guide TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C) 01 mar 2005
Application note TMS320DM64x Power Consumption Summary (Rev. F) 18 feb 2005
User guide TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B) 25 ene 2005
Application note Use and Handling of Semiconductor Packages With ENIG Pad Finishes 31 ago 2004
User guide TMS320C6000 Chip Support Library API Reference Guide (Rev. J) 13 ago 2004
Application note High Resolution Video Using the DM642 DSP and the THS8200 Driver (Rev. A) 03 may 2004
Application note Interfacing an LCD Controller to a DM642 Video Port (Rev. B) 03 may 2004
Application note TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D) 26 abr 2004
Application note TMS320C6000 Board Design: Considerations for Debug (Rev. C) 21 abr 2004
User guide TMS320C6000 DSP EMAC/MDIO Module Reference Guide (Rev. A) 26 mar 2004
User guide TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (Rev. A) 25 mar 2004
Application note TMS320C6000 McBSP Initialization (Rev. C) 08 mar 2004
Application note TMS320C6000 EDMA IO Scheduling and Performance 05 mar 2004
More literature Video/Imaging Benchmarks (Rev. A) 01 mar 2004
Product overview Video Security over IP (VSIP) Development Platform Product Bulletin 05 nov 2003
User guide TMS320C6000 DSP Designing for JTAG Emulation Reference Guide 31 jul 2003
Product overview TMS320DM64x Digital Media Development Tools Product Bulletin 31 jul 2003
User guide TMS320C6000 DSP Cache User's Guide (Rev. A) 05 may 2003
Application note Using IBIS Models for Timing Analysis (Rev. A) 15 abr 2003
Application note TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B) 04 jun 2002
Application note TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C) 17 abr 2002
Application note TMS320C6000 Board Design for JTAG (Rev. C) 02 abr 2002
Application note TMS320C6000 EMIF to External Flash Memory (Rev. A) 13 feb 2002
Application note Cache Usage in High-Performance DSP Applications with the TMS320C64x 13 dic 2001
Application note Using a TMS320C6000 McBSP for Data Packing (Rev. A) 31 oct 2001
Application note TMS320C6000 Enhanced DMA: Example Applications (Rev. A) 24 oct 2001
Application note Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A) 30 sep 2001
Application note TMS320C6000 Host Port to MC68360 Interface (Rev. A) 30 sep 2001
Application note TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A) 31 ago 2001
Application note TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A) 31 ago 2001
Application note Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A) 31 ago 2001
Application note TMS320C6000 System Clock Circuit Example (Rev. A) 15 ago 2001
Application note TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A) 23 jul 2001
Application note TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A) 10 jul 2001
Application note TMS320C6000 McBSP: Interface to SPI ROM (Rev. C) 30 jun 2001
Application note TMS320C6000 Host Port to MPC860 Interface (Rev. A) 21 jun 2001
Application note TMS320C6000 McBSP: IOM-2 Interface (Rev. A) 21 may 2001
User guide TMS320C64x Technical Overview (Rev. B) 30 ene 2001
Application note Circular Buffering on TMS320C6000 (Rev. A) 12 sep 2000
Application note TMS320C6000 McBSP as a TDM Highway (Rev. A) 11 sep 2000
Application note TMS320C6000 u-Law and a-Law Companding with Software or the McBSP 02 feb 2000
Application note General Guide to Implement Logarithmic and Exponential Operations on Fixed-Point 31 ene 2000
Application note TMS320C6000 C Compiler: C Implementation of Intrinsics 07 dic 1999
Application note TMS320C6000 McBSP: I2S Interface 08 sep 1999

Diseño y desarrollo

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Sonda de depuración

TMDSEMU200-U — Sonda de depuración XDS200 USB

El XDS200 es una sonda de depuración (emulador) que se utiliza para depurar dispositivos integrados de TI. El XDS200 presenta un equilibrio de bajo costo con buen rendimiento en comparación con el XDS110 de bajo costo y el XDS560v2 de alto rendimiento. Es compatible con una amplia (...)

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TMDSEMU560V2STM-U — Sonda de depuración USB de seguimiento del sistema XDS560v2

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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Sonda de depuración

TMDSEMU560V2STM-UE — Sonda de depuración USB y ethernet de seguimiento del sistema XDS560v2

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

No disponible en TI.com
Controlador o biblioteca

SPRC090 — Download TMS320C6000 Chip Support Library

The Chip Support Library (CSL) provides an application programming interface (API) used for configuring and controlling the DSP on-chip peripherals for ease of use, compatibility between various C6000 devices and hardware abstraction. This will shorten development time by providing standardization (...)
Productos y hardware compatibles

Productos y hardware compatibles

Productos
Procesadores digitales de señales (DSP)
TMS320C6412 — DSP de punto fijo C64x de hasta 720 MHz, con McBSP, McASP, I2cC y Ethernet TMS320C6414 — DSP de punto fijo C64x de hasta 720 MHz, McBSP TMS320C6414T — DSP de punto fijo C64x de hasta 1 GHz y McBSP TMS320C6415 — DSP de punto fijo C64x de hasta 720 MHz, con McBSP y PCI TMS320C6415T — DSP de punto fijo C64x de hasta 850 MHz, con McBSP y PCI TMS320C6416 — DSP de punto fijo C64x de hasta 720 MHz, con McBSP, PCI y VCP/TCP TMS320C6416T — DSP de punto fijo C64x de hasta 850 MHz, con McBSP, PCI y VCP/TCP TMS320C6701 — DSP de punto flotante C67x de hasta 167 MHz, con McBSP TMS320DM640 — Procesador de señal digital de punto fijo de imágenes y video TMS320DM641 — Procesador de señal digital de punto fijo de imágenes y video TMS320DM642 — Procesador de señal digital de punto fijo de imágenes y video TMS320DM642Q — Procesador de señal digital de punto fijo de imágenes y video
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Controlador o biblioteca

SPRC122 — C62x/C64x Fast Run-Time Support Library

The C62x/64x FastRTS Library is an optimized, floating-point function library for C programmers using either TMS320C62x or TMS320C64x devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By replacing the current (...)

Productos y hardware compatibles

Productos y hardware compatibles

Productos
Procesadores digitales de señales (DSP)
SM320C6201-EP — DSP de punto fijo C6201 de producto mejorado SM320C6455-EP — DSP de punto fijo C6455 de producto mejorado SMJ320C6201B — Procesador de señal digital de punto fijo, de calidad militar SMJ320C6203 — DSP de punto fijo de calidad militar C62x: encapsulado cerámico TMS320C6202B — DSP de punto fijo C62x de hasta 300 MHz y 384 KB TMS320C6203B — DSP de punto fijo C62x de hasta 300 MHz y 896 KB TMS320C6204 — Procesador de señal digital de punto fijo TMS320C6205 — Procesador de señal digital de punto fijo TMS320C6211B — DSP de punto fijo C62x de hasta 167 MHz TMS320C6412 — DSP de punto fijo C64x de hasta 720 MHz, con McBSP, McASP, I2cC y Ethernet TMS320C6414 — DSP de punto fijo C64x de hasta 720 MHz, McBSP TMS320C6414T — DSP de punto fijo C64x de hasta 1 GHz y McBSP TMS320C6415 — DSP de punto fijo C64x de hasta 720 MHz, con McBSP y PCI TMS320C6415T — DSP de punto fijo C64x de hasta 850 MHz, con McBSP y PCI TMS320C6416 — DSP de punto fijo C64x de hasta 720 MHz, con McBSP, PCI y VCP/TCP TMS320C6416T — DSP de punto fijo C64x de hasta 850 MHz, con McBSP, PCI y VCP/TCP TMS320C6421 — DSP de punto fijo C64x+ de hasta 600 MHz, EMIFA de 8 bits, DDR2 de 16 bits y SDRAM TMS320C6421Q — DSP de punto fijo C64x+ de hasta 600 MHz, EMIFA de 8 bits y DDR2 de 16 bits TMS320C6424 — DSP de punto fijo C64x+ de hasta 600 MHz, EMIFA de 16/8 bits, DDR2 de 32/16 bits y SDRAM TMS320C6424Q — DSP de punto fijo C64x+ de hasta 600 MHz, EMIFA de 16/8 bits y DDR2 de 32/16 bits TMS320C6452 — DSP de punto fijo C64x+ de hasta 900 MHz, con Ethernet de 1 Gbps TMS320C6454 — DSP de punto fijo C64x+ de hasta 1 GHz, con EMIFA de 64 bits, DDR2 de 32/16 bits y Ethernet de 1 Gbp TMS320C6455 — Procesador de señal digital (DSP) de punto fijo C64x+ de hasta 1.2 GHz, interfaz de memoria externa TMS320C6457 — Procesador de señal digital de infraestructura de comunicaciones TMS320C6474 — Procesador de señal digital multinúcleo TMS320DM640 — Procesador de señal digital de punto fijo de imágenes y video TMS320DM641 — Procesador de señal digital de punto fijo de imágenes y video TMS320DM642 — Procesador de señal digital de punto fijo de imágenes y video TMS320DM642Q — Procesador de señal digital de punto fijo de imágenes y video TMS320DM6431 — Procesador de medios digitales TMS320DM6431Q — Procesador de medios digitales de hasta 2,400 MIPS y velocidad de reloj de 300 MHz TMS320DM6433 — Procesador de medios digitales TMS320DM6435 — Procesador de medios digitales TMS320DM6435Q — Procesador de medios digitales de hasta 4.800 MIPS y velocidad de reloj de 600 MHz, 1 McASP y 1 McBS TMS320DM6437 — Procesador de medios digitales TMS320DM6437Q — Procesador de medios digitales de hasta 4800 MIPS y velocidad de reloj de 600 MHz con 1 McASP y 2 Mc TMS320DM6441 — Sistema en chip de medios digitales DaVinci TMS320DM6443 — Sistema en chip de medios digitales DaVinci TMS320DM6446 — Sistema en chip de medios digitales DaVinci
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Controlador o biblioteca

TELECOMLIB — Bibliotecas de telecomunicaciones y medios: FAXLIB, VoLIB y AEC/AER para procesadores TMS320C64x+ y

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
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Modelo de simulación

DM641 GDK BSDL Model

SPRM134.ZIP (9 KB) - BSDL Model
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Modelo de simulación

DM641 GDK/GNZ IBIS Model

SPRM125.ZIP (106 KB) - IBIS Model
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Modelo de simulación

DM641 GNZ BSDL Model

SPRM131.ZIP (9 KB) - BSDL Model
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Encapsulado Pines Símbolos CAD, huellas y modelos 3D
OMFCBGA (ZNZ) 548 Ultra Librarian
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