TMS320VC5402

Name: TMS320VC5402
Brand: TI
SKU: TMS320VC5402
Price: 6.513 USD

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Procesador de señal digital

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Hoja de datos

document-pdfAcrobat TMS320VC5402 Fixed-Point Digital Signal Processor datasheet (Rev. G) (Inglés)

Errata

document-pdfAcrobat
TMS320UC5402/TMS320VC5402 Digital Signal Processors Silicon Errata (Rev. D) (Inglés)

TMS320VC5402

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Detalles del producto

DSP type

1 C54x

DSP (max) (MHz)

100

CPU

16-bit

Operating system

DSP/BIOS

Rating

Catalog

Operating temperature range (°C)

0 to 0

DSP type

1 C54x

DSP (max) (MHz)

100

CPU

16-bit

Operating system

DSP/BIOS

Rating

Catalog

Operating temperature range (°C)

0 to 0

LQFP (PGE)

144

484 mm² 22 x 22

Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
40-Bit Arithmetic Logic Unit (ALU), Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
17-× 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
Data Bus With a Bus-Holder Feature
Extended Addressing Mode for 1M × 16-Bit Maximum Addressable External Program Space
4K x 16-Bit On-Chip ROM
16K x 16-Bit Dual-Access On-Chip RAM
Single-Instruction-Repeat and Block-Repeat Operations for Program Code
Block-Memory-Move Instructions for Efficient Program and Data Management
Instructions With a 32-Bit Long Word Operand
Instructions With Two- or Three-Operand Reads
Arithmetic Instructions With Parallel Store and Parallel Load
Conditional Store Instructions
Fast Return From Interrupt
On-Chip Peripherals
- Software-Programmable Wait-State Generator and Programmable Bank Switching
- On-Chip Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source
- Two Multichannel Buffered Serial Ports (McBSPs)
- Enhanced 8-Bit Parallel Host-Port Interface (HPI8)
- Two 16-Bit Timers
- Six-Channel Direct Memory Access (DMA) Controller
Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG) Boundary Scan Logic
10-ns Single-Cycle Fixed-Point Instruction Execution Time (100 MIPS) for 3.3-V Power Supply (1.8-V Core)
Available in a 144-Pin Plastic Low-Profile Quad Flatpack (LQFP) (PGE Suffix) and a 144-Pin Ball Grid Array (BGA) (GGU Suffix)

All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
NOTE:This data sheet is designed to be used in conjunction with the TMS320C5000 DSP Family Functional Overview (literature number SPRU307).

Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
40-Bit Arithmetic Logic Unit (ALU), Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
17-× 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
Data Bus With a Bus-Holder Feature
Extended Addressing Mode for 1M × 16-Bit Maximum Addressable External Program Space
4K x 16-Bit On-Chip ROM
16K x 16-Bit Dual-Access On-Chip RAM
Single-Instruction-Repeat and Block-Repeat Operations for Program Code
Block-Memory-Move Instructions for Efficient Program and Data Management
Instructions With a 32-Bit Long Word Operand
Instructions With Two- or Three-Operand Reads
Arithmetic Instructions With Parallel Store and Parallel Load
Conditional Store Instructions
Fast Return From Interrupt
On-Chip Peripherals
- Software-Programmable Wait-State Generator and Programmable Bank Switching
- On-Chip Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source
- Two Multichannel Buffered Serial Ports (McBSPs)
- Enhanced 8-Bit Parallel Host-Port Interface (HPI8)
- Two 16-Bit Timers
- Six-Channel Direct Memory Access (DMA) Controller
Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes
CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1 (JTAG) Boundary Scan Logic
10-ns Single-Cycle Fixed-Point Instruction Execution Time (100 MIPS) for 3.3-V Power Supply (1.8-V Core)
Available in a 144-Pin Plastic Low-Profile Quad Flatpack (LQFP) (PGE Suffix) and a 144-Pin Ball Grid Array (BGA) (GGU Suffix)

All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
NOTE:This data sheet is designed to be used in conjunction with the TMS320C5000 DSP Family Functional Overview (literature number SPRU307).

The TMS320VC5402 fixed-point, digital signal processor (DSP) (hereafter referred to as the '5402 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.

Separate program and data spaces allow simultaneous access to program instructions and data, providing the high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can be performed in a single machine cycle. In addition, the '5402 includes the control mechanisms to manage interrupts, repeated operations, and function calls.

The TMS320VC5402 fixed-point, digital signal processor (DSP) (hereafter referred to as the '5402 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.

Separate program and data spaces allow simultaneous access to program instructions and data, providing the high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can be performed in a single machine cycle. In addition, the '5402 includes the control mechanisms to manage interrupts, repeated operations, and function calls.

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Documentación técnica

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	Tipo	Título		Fecha
*	Data sheet	TMS320VC5402 Fixed-Point Digital Signal Processor datasheet (Rev. G)		20 oct 2008
*	Errata	TMS320UC5402/TMS320VC5402 Digital Signal Processors Silicon Errata (Rev. D)		10 abr 2003
	White paper	Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A)	PDF \| HTML	30 abr 2024
	Application note	TMS320VC5402 and TMS320UC5402 Bootloader (Rev. B)		03 nov 2004
	User guide	TMS320C54x Chip Support Library API Reference Guide (Rev. D)		05 may 2003
	Application note	Using the TMS320C5402 DSK Sine Program and evmdsk54x.dll		11 nov 2002
	Application note	Interfacing the TLV320AIC12/13/14/15 Codec to the TMS320C5402? DSP		24 oct 2002
	Application note	Bootloading the TMS320VC5402 in HPI Mode		29 abr 2002
	User guide	TMS320C54x DSP CPU and Peripherals Reference Set Volume 1 (Rev. G)		31 mar 2001
	User guide	TMS320C54x DSP Algebraic Instruction Set Reference Set Volume 3 (Rev. C)		31 ene 2001
	User guide	TMS320C54x DSP Mnemonic Instruction Set Reference Set Volume 2 (Rev. C)		31 ene 2001
	Application note	Interfacing the TLV320AIC10/11 Codec to the TMS320C5402 DSP		18 dic 2000
	Application note	Powering the TMS320VC5402 DSP Using the TPS60100, TPS76918, and the TPS3305-18		16 dic 1999
	Application note	TPS6010x/TPS6011x Charge Pump (Rev. A)		16 dic 1999
	User guide	TMS320C54x DSP Applications Guide Reference Set Volume 4		01 oct 1996

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

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Sonda de depuración

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The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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Sonda de depuración

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The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)