製品詳細

2nd harmonic (dBc) 78 3rd harmonic (dBc) 75 Frequency of harmonic distortion measurement (MHz) 200 Acl, min spec gain (V/V) 0.5 Architecture Fully Differential ADC Driver, VGA BW at Acl (MHz) 1400 Gain (max) (dB) 25.74 Gain (min) (dB) -4.3 Step size (dB) 0.2 Type RF VGA Iq per channel (typ) (mA) 116 Number of channels 4 Rating Catalog Operating temperature range (°C) -40 to 85 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.25 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 4.75 Vs (min) (V) 4.75 Vs (max) (V) 5.25
2nd harmonic (dBc) 78 3rd harmonic (dBc) 75 Frequency of harmonic distortion measurement (MHz) 200 Acl, min spec gain (V/V) 0.5 Architecture Fully Differential ADC Driver, VGA BW at Acl (MHz) 1400 Gain (max) (dB) 25.74 Gain (min) (dB) -4.3 Step size (dB) 0.2 Type RF VGA Iq per channel (typ) (mA) 116 Number of channels 4 Rating Catalog Operating temperature range (°C) -40 to 85 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.25 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 4.75 Vs (min) (V) 4.75 Vs (max) (V) 5.25
WQFN (NJY) 54 55 mm² 10 x 5.5
  • OIP3: 49dBm at 200MHz
  • Noise Figure: 8.5dB
  • Voltage Gain: 26dB
  • 1dB Gain Steps
  • Enable pins active in SPI mode
  • −3dB bandwidth of 1400 MHz
  • Gain Step Accuracy: 0.2 dB
  • Disable function for each channel
  • Parallel and Serial gain control
  • Low Power Mode for power management flexibility
  • Small footprint LLP package
  • OIP3: 49dBm at 200MHz
  • Noise Figure: 8.5dB
  • Voltage Gain: 26dB
  • 1dB Gain Steps
  • Enable pins active in SPI mode
  • −3dB bandwidth of 1400 MHz
  • Gain Step Accuracy: 0.2 dB
  • Disable function for each channel
  • Parallel and Serial gain control
  • Low Power Mode for power management flexibility
  • Small footprint LLP package

The LMH6523 contains four, high performance, digitally controlled variable gain amplifiers (DVGA). It has been designed for use in narrowband and broadband IF sampling applications. Typically, the LMH6523 drives a high performance ADC in a broad range of mixed signal and digital communication applications such as mobile radio and cellular base stations where automatic gain control (AGC) is required to increase system dynamic range.

Each channel of LMH6523 has an independent, digitally controlled attenuator and a high linearity, differential output, amplifier. All circuitry has been optimized for low distortion and maximum system design flexibility. Power consumption is managed by a three-state enable pin. Individual channels can be disabled or placed into a Low Power Mode or a higher performance, High Power Mode. The enable pin is active in both serial and parallel modes for systems that require high speed power control.

The LMH6523 digitally controlled attenuator provides precise 1dB gain steps over a 31dB range. The digital attenuator can be controlled by either a SPI Serial bus or a high speed parallel bus.

The output amplifier has a differential output, allowing large signal swings on a single 5V supply. The low impedance output provides maximum flexibility when driving a wide range filter designs or analog to digital converters. For applications which have very large changes in signal level LMH6523 can support up to 62dB of gain range by cascading channels.

The LMH6523 operates over the industrial temperature range of −40°C to 85°C. The LMH6523 is available in a 54-Pin, thermally enhanced, LLP package.

The LMH6523 contains four, high performance, digitally controlled variable gain amplifiers (DVGA). It has been designed for use in narrowband and broadband IF sampling applications. Typically, the LMH6523 drives a high performance ADC in a broad range of mixed signal and digital communication applications such as mobile radio and cellular base stations where automatic gain control (AGC) is required to increase system dynamic range.

Each channel of LMH6523 has an independent, digitally controlled attenuator and a high linearity, differential output, amplifier. All circuitry has been optimized for low distortion and maximum system design flexibility. Power consumption is managed by a three-state enable pin. Individual channels can be disabled or placed into a Low Power Mode or a higher performance, High Power Mode. The enable pin is active in both serial and parallel modes for systems that require high speed power control.

The LMH6523 digitally controlled attenuator provides precise 1dB gain steps over a 31dB range. The digital attenuator can be controlled by either a SPI Serial bus or a high speed parallel bus.

The output amplifier has a differential output, allowing large signal swings on a single 5V supply. The low impedance output provides maximum flexibility when driving a wide range filter designs or analog to digital converters. For applications which have very large changes in signal level LMH6523 can support up to 62dB of gain range by cascading channels.

The LMH6523 operates over the industrial temperature range of −40°C to 85°C. The LMH6523 is available in a 54-Pin, thermally enhanced, LLP package.

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種類 タイトル 最新の英語版をダウンロード 日付
* データシート LMH6523 High Performance Quad DVGA データシート 2012年 10月 24日
e-Book(PDF) The Signal - オペアンプ設計ブログ集 英語版 2018年 3月 23日

設計および開発

その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。

評価ボード

LMH6522EVAL — LMH6522EVAL 評価モジュール

The LMH6522EVAL evaluation board is designed to facilitate the test and measurement of the LMH6522 quad, digitally controlled, variable gain amplifier (DVGA). This board is configured with 50 Ohm, single ended signal paths for use with standard lab equipment. The LMH6522EVAL board offers switch (...)
ユーザー ガイド: PDF
シミュレーション・モデル

LMH6523 PSpice Model

SNOM714.ZIP (192 KB) - PSpice Model
シミュレーション・モデル

LMH6523 TINA-TI Reference Design

SNOM337.TSC (2539 KB) - TINA-TI Reference Design
シミュレーション・モデル

LMH6523 TINA-TI Spice Model

SNOM338.ZIP (11 KB) - TINA-TI Spice Model
パッケージ ピン数 CAD シンボル、フットプリント、および 3D モデル
WQFN (NJY) 54 Ultra Librarian

購入と品質

記載されている情報:
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用原材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報:
  • ファブの拠点
  • 組み立てを実施した拠点

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