제품 상세 정보

Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 16 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type TTL Output type CMOS Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Technology family ACT Rating Catalog Operating temperature range (°C) -40 to 85
Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 16 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type TTL Output type CMOS Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Technology family ACT Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DL) 48 164.358 mm² 15.88 x 10.35 TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1
  • Members of the Texas Instruments WidebusTM Family
  • Inputs Are TTL-Voltage Compatible
  • 3-State Outputs Drive Bus Lines Directly
  • Flow-Through Architecture Optimizes PCB Layout
  • Distributed VCC and GND Configuration to Minimize High-Speed Switching Noise
  • EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
  • 500-mA Typical Latch-Up Immunity at 125°C
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings, Thin Shrink Small-Outline (DGG) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings

 

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

  • Members of the Texas Instruments WidebusTM Family
  • Inputs Are TTL-Voltage Compatible
  • 3-State Outputs Drive Bus Lines Directly
  • Flow-Through Architecture Optimizes PCB Layout
  • Distributed VCC and GND Configuration to Minimize High-Speed Switching Noise
  • EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
  • 500-mA Typical Latch-Up Immunity at 125°C
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings, Thin Shrink Small-Outline (DGG) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings

 

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

The SN54ACT16245 and 74ACT16245 are 16-bit bus transceivers organized as dual-octal noninverting 3-state transceivers and designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The enable (G\) input can be used to disable the devices so that the buses are effectively isolated.

The SN54ACT16245 is characterized for operation over the full military temperature range of -55°C to 125°C. The 74ACT16245 is characterized for operation from -40°C to 85°C.

 

 

The SN54ACT16245 and 74ACT16245 are 16-bit bus transceivers organized as dual-octal noninverting 3-state transceivers and designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The enable (G\) input can be used to disable the devices so that the buses are effectively isolated.

The SN54ACT16245 is characterized for operation over the full military temperature range of -55°C to 125°C. The 74ACT16245 is characterized for operation from -40°C to 85°C.

 

 

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관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치와 유사한 기능
SN74ACT245 활성 TTL 호환 CMOS 입력 및 3상 출력을 지원하는 옥탈 버스 트랜시버 Voltage range (4.5V to 5.5V), average drive strength (24mA), average propagation delay (8ns)

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
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11개 모두 보기
유형 직함 날짜
* Data sheet 16-Bit Bus Transceivers With 3-State Outputs datasheet (Rev. B) 1996/04/01
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997/06/01
Application note Designing With Logic (Rev. C) 1997/06/01
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996/04/01

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

패키지 CAD 기호, 풋프린트 및 3D 모델
SSOP (DL) 48 Ultra Librarian
TSSOP (DGG) 48 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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