CD40109B-Q1

활성

차량용 카탈로그 CMOS 쿼드 저압-To-고압 레벨 시프터(20V 정격)

제품 상세 정보

Technology family CD4000 Bits (#) 4 Configuration 4 Ch A to B 0 Ch B to A High input voltage (min) (V) 3 High input voltage (max) (V) 18 Vout (min) (V) 0 Vout (max) (V) 18 Data rate (max) (Mbps) 24 IOH (max) (mA) -6.8 IOL (max) (mA) -6.8 Supply current (max) (µA) 18 Features 54.59, 79.56 Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Automotive Operating temperature range (°C) -40 to 125
Technology family CD4000 Bits (#) 4 Configuration 4 Ch A to B 0 Ch B to A High input voltage (min) (V) 3 High input voltage (max) (V) 18 Vout (min) (V) 0 Vout (max) (V) 18 Data rate (max) (Mbps) 24 IOH (max) (mA) -6.8 IOL (max) (mA) -6.8 Supply current (max) (µA) 18 Features 54.59, 79.56 Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Automotive Operating temperature range (°C) -40 to 125
SOP (NS) 16 79.56 mm² 10.2 x 7.8
  • Qualified for Automotive Applications
  • Independent of Power Supply Sequence Considerations
    • VCC Can Exceed VDD
    • Input Signals can Exceed Both VCC and VDD
  • Up and Down Level-Shifting Capability
  • Three-State Outputs With Separate Enable Controls
  • Standardized Symmetrical Output Characteristics
  • 100% Tested for Quiescent Current at 20 V
  • Maximum Input Current:
    • 1 µA at 18 V Over Full Package-Temperature Range
    • 100 nA at 18 V and 25°C
  • Noise Margin (Full Package-Temperature Range):
    • 1 V at VCC = 5 V, VDD = 10 V
    • 2 V at VCC = 10 V, VDD = 15 V
  • 5-V, 10-V, and 15-V Parametric Ratings
  • Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard specifications for Description of ’B’ Series CMOS Devices"
  • Latch-Up Performance Meets 50 mA per JESD 78, Class I
  • APPLICATIONS
    • High-or-Low Level-Shifting With Three-State Outputs for Unidirectional or Bidirectional Bussing
    • Isolation of Logic Subsystem Using Separate Power Supplies from Supply Sequencing, Supply Loss, and Supply Regulation Considerations

  • Qualified for Automotive Applications
  • Independent of Power Supply Sequence Considerations
    • VCC Can Exceed VDD
    • Input Signals can Exceed Both VCC and VDD
  • Up and Down Level-Shifting Capability
  • Three-State Outputs With Separate Enable Controls
  • Standardized Symmetrical Output Characteristics
  • 100% Tested for Quiescent Current at 20 V
  • Maximum Input Current:
    • 1 µA at 18 V Over Full Package-Temperature Range
    • 100 nA at 18 V and 25°C
  • Noise Margin (Full Package-Temperature Range):
    • 1 V at VCC = 5 V, VDD = 10 V
    • 2 V at VCC = 10 V, VDD = 15 V
  • 5-V, 10-V, and 15-V Parametric Ratings
  • Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard specifications for Description of ’B’ Series CMOS Devices"
  • Latch-Up Performance Meets 50 mA per JESD 78, Class I
  • APPLICATIONS
    • High-or-Low Level-Shifting With Three-State Outputs for Unidirectional or Bidirectional Bussing
    • Isolation of Logic Subsystem Using Separate Power Supplies from Supply Sequencing, Supply Loss, and Supply Regulation Considerations

CD40109B contains four low-to-high-voltage level-shifting circuits. Each circuit will shift a low-voltage digital-logic input signal (A, B, C, D) with logical 1 = VCC and logical 0 = VSS to a high-voltage output signal (E, F, G, H) with logical 1 = VDD and logical 0 = VSS.

The RCA-CD40109, unlike other low-to-high level-shifting circuits, does not require the presence of the high-voltage supply (VDD) before the application of either the low-voltage supply (VCC) or the input signals. There are no restrictions on the sequence of application of VDD, VCC, or the input signals. In addition, with one exception there are no restrictions on the relative magnitudes of the supply voltages or input signals within the device maximum ratings, provided that the input signal swings between VSS and at least 0.7 VCC; VCC may exceed VDD, and input signals may exceed VCC and VDD. When operated in the mode VCC > VDD, the CD40109 will operate as a high-to-low level-shifter.

The CD40109 also features individual three-state output capability. A low level on any of the separately enabled three-state output controls produces a high-impedance state in the corresponding output.

CD40109B contains four low-to-high-voltage level-shifting circuits. Each circuit will shift a low-voltage digital-logic input signal (A, B, C, D) with logical 1 = VCC and logical 0 = VSS to a high-voltage output signal (E, F, G, H) with logical 1 = VDD and logical 0 = VSS.

The RCA-CD40109, unlike other low-to-high level-shifting circuits, does not require the presence of the high-voltage supply (VDD) before the application of either the low-voltage supply (VCC) or the input signals. There are no restrictions on the sequence of application of VDD, VCC, or the input signals. In addition, with one exception there are no restrictions on the relative magnitudes of the supply voltages or input signals within the device maximum ratings, provided that the input signal swings between VSS and at least 0.7 VCC; VCC may exceed VDD, and input signals may exceed VCC and VDD. When operated in the mode VCC > VDD, the CD40109 will operate as a high-to-low level-shifter.

The CD40109 also features individual three-state output capability. A low level on any of the separately enabled three-state output controls produces a high-impedance state in the corresponding output.

다운로드

관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
CD40109B 활성 CMOS 쿼드 저전압-고전압 레벨 시프터(20V 정격) Similar product not rated for automotive applications
비교 대상 장치와 유사한 기능
TXH0137D-Q1 미리 보기 오픈 드레인 출력을 지원하는 오토모티브, 고정 방향, 7비트 30V 전압 레벨 변환기 Automotive qualified and higher voltage range with open drain output

기술 자료

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유형 직함 날짜
* Data sheet CD40109B-Q1 CMOS Quad Low-to-High Voltage Level Shifter datasheet (Rev. A) 2011/08/24

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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