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Technology family HC Rating Catalog Operating temperature range (°C) -55 to 125
Technology family HC Rating Catalog Operating temperature range (°C) -55 to 125
PDIP (N) 16 181.42 mm² 19.3 x 9.4 SOIC (D) 16 59.4 mm² 9.9 x 6
  • Independent Asynchronous Inputs and Outputs
  • Expandable in Either Direction
  • Reset Capability
  • Status Indicators on Inputs and Outputs
  • Three-State Outputs
  • Shift-Out Independent of Three-State Control
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . -55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
  • Applications
    • Bit-Rate Smoothing
    • CPU/Terminal Buffering
    • Data Communications
    • Peripheral Buffering
    • Line Printer Input Buffers
    • Auto-Dialers
    • CRT Buffer Memories
    • Radar Data Acquisition
  • Independent Asynchronous Inputs and Outputs
  • Expandable in Either Direction
  • Reset Capability
  • Status Indicators on Inputs and Outputs
  • Three-State Outputs
  • Shift-Out Independent of Three-State Control
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . -55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
  • Applications
    • Bit-Rate Smoothing
    • CPU/Terminal Buffering
    • Data Communications
    • Peripheral Buffering
    • Line Printer Input Buffers
    • Auto-Dialers
    • CRT Buffer Memories
    • Radar Data Acquisition

The ’HC40105 and ’HCT40105 are high-speed silicon-gate CMOS devices that are compatible, except for "shift-out" circuitry, with the CD40105B. They are low-power first-in-out (FIFO) "elastic" storage registers that can store 16 four-bit words. The 40105 is capable of handling input and output data at different shifting rates. This feature makes particularly useful as a buffer between asynchronous systems.

Each work position in the register is clocked by a control flip-flop, which stores a marker bit. A "1" signifies that the position’s data is filled and a "0" denotes a vacancy in that position. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip-flop is in the "0" state and sees a "1" in the preceeding flip-flop, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding flip-flop to "0". The first and last control flip-flops have buffered outputs. Since all empty locations "bubble" automatically to the input end, and all valid data ripple through to the output end, the status of the first control flip-flop (DATA-IN READY) indicates if the FIFO is full, and the status of the last flip-flop (DATA-OUT READY) indicates if the FIFO contains data. As the earliest data are removed from the bottom of the data stack (the output end), all data entered later will automatically propagate (ripple) toward the output.

The ’HC40105 and ’HCT40105 are high-speed silicon-gate CMOS devices that are compatible, except for "shift-out" circuitry, with the CD40105B. They are low-power first-in-out (FIFO) "elastic" storage registers that can store 16 four-bit words. The 40105 is capable of handling input and output data at different shifting rates. This feature makes particularly useful as a buffer between asynchronous systems.

Each work position in the register is clocked by a control flip-flop, which stores a marker bit. A "1" signifies that the position’s data is filled and a "0" denotes a vacancy in that position. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip-flop is in the "0" state and sees a "1" in the preceeding flip-flop, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding flip-flop to "0". The first and last control flip-flops have buffered outputs. Since all empty locations "bubble" automatically to the input end, and all valid data ripple through to the output end, the status of the first control flip-flop (DATA-IN READY) indicates if the FIFO is full, and the status of the last flip-flop (DATA-OUT READY) indicates if the FIFO contains data. As the earliest data are removed from the bottom of the data stack (the output end), all data entered later will automatically propagate (ripple) toward the output.

다운로드

관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치와 유사한 기능
CD74HC4094 활성 3단계 출력을 지원하는 고속 CMOS 로직 8단계 시프트-및-저장 버스 레지스터 Voltage range (2V to 6V), average drive strength (8mA), average propagation delay (20ns)

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유형 직함 날짜
* Data sheet CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105 datasheet (Rev. C) 2003/10/16

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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