DS25BR120
- DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation
- Four Levels of Transmit Pre-Emphasis Drive Lossy Backplanes and Cables
- On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space
- 7 kV ESD on LVDS I/O pins Protects Adjoining Components
- Small 3 mm x 3 mm 8-WSON Space Saving Package
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The DS25BR120 is a single channel 3.125 Gbps LVDS buffer optimized for high-speed signal transmission over lossy FR-4 printed circuit board backplanes and balanced metallic cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity.
The DS25BR120 features four levels of pre-emphasis (PE) for use as an optimized driver device. Other LVDS devices with similar IO characteristics include the following products. The DS25BR110 features four levels of equalization for use as an optimized receiver device, while the DS25BR100 features both pre-emphasis and equalization for use as an optimized repeater device. The DS25BR150 is a buffer/repeater with the lowest power consumption and does not feature transmit pre-emphasis nor receive equalization.
Wide input common mode range allows the receiver to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires minimal space on the board while the flow-through pinout allows easy board layout. The differential inputs and outputs are internally terminated with a 100Ω resistor to lower device input and output return losses, reduce component count and further minimize board space.
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | DS25BR120 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis datasheet (Rev. E) | 2013/04/14 | |
| Application note | Applications of Low-Voltage Differential Signaling (LVDS) in LED Walls | 2020/10/29 | ||
| Application note | Applications of Low-Voltage Differential Signaling (LVDS) in Ultrasound Scanners | 2019/06/29 | ||
| Application note | LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A) | 2013/04/29 | ||
| Application note | AN-1957 LVDS Signal Conditioners Reduce Data-Dependent Jitter (Rev. A) | 2013/04/26 | ||
| User guide | 3.125 Gbps LVDS Buffers with Pre-emphasis and Equalization User Guide | 2012/01/25 |
설계 및 개발
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DS25BR100EVK — 3.125Gbps LVDS 단일 채널 버퍼, 전송 사전 강조 및 수신 이퀄라이제이션 제품군
The DS25BR100EVK is an evaluation kit designed for demonstrating performance of the 3.125 Gbps LVDS Single Channel Buffers with Transmit Pre-Emphasis (PE) and Receive Equalization (EQ) family (DS25BR100, DS25BR110 and DS25BR120). The evaluation kit provides all three devices on a single board and (...)
PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®
TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| WSON (NGQ) | 8 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
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