인터페이스 PCIe, SAS 및 SATA IC

DS50PCI402

활성

이퀄라이제이션 및 디엠퍼시스 기능을 갖춘 2.5/5.0Gbps 4레인 PCI Express 리드라이버

제품 상세 정보

Type Redriver Protocols General purpose, PCIe1, PCIe2, sRIO Applications Backplane, Front Port, Peripheral I/O Number of channels 8 Speed (max) (Gbpp) 5 Supply voltage (V) 2.5 Rating Catalog Operating temperature range (°C) -10 to 85
Type Redriver Protocols General purpose, PCIe1, PCIe2, sRIO Applications Backplane, Front Port, Peripheral I/O Number of channels 8 Speed (max) (Gbpp) 5 Supply voltage (V) 2.5 Rating Catalog Operating temperature range (°C) -10 to 85
WQFN (NJY) 54 55 mm² 10 x 5.5
  • Input and Output signal conditioning increases PCIe reach in backplanes and cables
  • 0.09 UI of residual deterministic jitter at 5Gbps after 42” of FR4 (with Input EQ)
  • 0.11 UI of residual deterministic jitter at 5Gbps after 7m of PCIe Cable (with Input EQ)
  • 0.09 UI of residual deterministic jitter at 5Gbps with 28” of FR4 (with Output DE)
  • 0.13 UI of residual deterministic jitter at 5Gbps with 7m of PCIe Cable (with Output DE)
  • Adjustable Transmit VOD 800 to 1200mVp-p
  • Automatic and manual Receiver Detection and input termination control circuitry
  • Automatic power management on an individual lane basis via SMBus
  • Adjustable electrical idle detect threshold.
  • Data rate optimized 3-stage equalization to 27 dB gain
  • Data rate optimized 6-level 0 to 12 dB transmit de-emphasis
  • Flow-thru pinout in 10mmx5.5mm 54-pin leadless WQFN package
  • Single supply operation at 2.5V
  • >6kV HBM ESD rating
  • -10 to 85°C operating temperature range

All trademarks are the property of their respective owners.

  • Input and Output signal conditioning increases PCIe reach in backplanes and cables
  • 0.09 UI of residual deterministic jitter at 5Gbps after 42” of FR4 (with Input EQ)
  • 0.11 UI of residual deterministic jitter at 5Gbps after 7m of PCIe Cable (with Input EQ)
  • 0.09 UI of residual deterministic jitter at 5Gbps with 28” of FR4 (with Output DE)
  • 0.13 UI of residual deterministic jitter at 5Gbps with 7m of PCIe Cable (with Output DE)
  • Adjustable Transmit VOD 800 to 1200mVp-p
  • Automatic and manual Receiver Detection and input termination control circuitry
  • Automatic power management on an individual lane basis via SMBus
  • Adjustable electrical idle detect threshold.
  • Data rate optimized 3-stage equalization to 27 dB gain
  • Data rate optimized 6-level 0 to 12 dB transmit de-emphasis
  • Flow-thru pinout in 10mmx5.5mm 54-pin leadless WQFN package
  • Single supply operation at 2.5V
  • >6kV HBM ESD rating
  • -10 to 85°C operating temperature range

All trademarks are the property of their respective owners.

The DS50PCI402 is a low power, 4 lane bidirectional buffer/equalizer designed specifically for PCI Express Gen1 and Gen2 applications. The device performs both receive equalization and transmit de-emphasis, allowing maximum flexibility of physical placement within a system. The receiver is capable of opening an input eye that is completely closed due to inter-symbol interference (ISI) induced by the interconnect medium.

The transmitter de-emphasis level can be set by the user depending on the distance from the DS50PCI402 to the PCI Express endpoint. The DS50PCI402 contains PCI Express specific functions such as Transmit Idle, RX Detection, and Beacon signal pass through.

The device provides automatic receive detection circuitry which controls the input termination impedance. By automatically reflecting the current load impedance seen on the outputs back to the corresponding inputs the DS50PCI402 becomes completely transparent to both the PCIe root complex and endpoint. An internal rate detection circuit is included to detect if an incoming data stream is at Gen2 data rates, and adjusts the de-emphasis on it's output accordingly. The signal conditioning provided by the device allows systems to upgrade from Gen1 data rates to Gen2 without reducing their physical reach. This is true for FR4 applications such as backplanes, as well as cable interconnect.

The DS50PCI402 is a low power, 4 lane bidirectional buffer/equalizer designed specifically for PCI Express Gen1 and Gen2 applications. The device performs both receive equalization and transmit de-emphasis, allowing maximum flexibility of physical placement within a system. The receiver is capable of opening an input eye that is completely closed due to inter-symbol interference (ISI) induced by the interconnect medium.

The transmitter de-emphasis level can be set by the user depending on the distance from the DS50PCI402 to the PCI Express endpoint. The DS50PCI402 contains PCI Express specific functions such as Transmit Idle, RX Detection, and Beacon signal pass through.

The device provides automatic receive detection circuitry which controls the input termination impedance. By automatically reflecting the current load impedance seen on the outputs back to the corresponding inputs the DS50PCI402 becomes completely transparent to both the PCIe root complex and endpoint. An internal rate detection circuit is included to detect if an incoming data stream is at Gen2 data rates, and adjusts the de-emphasis on it's output accordingly. The signal conditioning provided by the device allows systems to upgrade from Gen1 data rates to Gen2 without reducing their physical reach. This is true for FR4 applications such as backplanes, as well as cable interconnect.

다운로드 스크립트와 함께 비디오 보기 동영상

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
2개 모두 보기
유형 직함 날짜
* Data sheet 2.5 / 5.0 Gbps 4 Lane PCI Express Repeater w/Equalization & De-Emphasis datasheet (Rev. H) 2013/03/04
User guide DS50PCI401EVK User Guide PCI Express SMA Evaluation Kit 2012/02/20

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

시뮬레이션 툴

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
시뮬레이션 툴

TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
사용 설명서: PDF
패키지 CAD 기호, 풋프린트 및 3D 모델
WQFN (NJY) 54 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

동영상