인터페이스 직렬 디지털 인터페이스(SDI) IC

LMH0030

활성

비디오 및 보조 데이터 FIFO 및 통합 케이블 드라이버가 포함된 SMPTE 292M/259M 디지털 비디오 시리얼라이저

제품 상세 정보

Function Serializer Supply voltage (V) 2.5, 3.3 Power consumption (mW) 430 Data rate (max) (Mbps) 1485 Control interface Pin/I2C Operating temperature range (°C) 0 to 70
Function Serializer Supply voltage (V) 2.5, 3.3 Power consumption (mW) 430 Data rate (max) (Mbps) 1485 Control interface Pin/I2C Operating temperature range (°C) 0 to 70
TQFP (PAG) 64 144 mm² 12 x 12
  • SDTV/HDTV Serial Digital Video Standard Compliant
  • Supports 270 Mbps, 360 Mbps, 540 Mbps, 1.4835Gbps and 1.485 Gbps SDV Data Rates with Auto-Detection
  • Low Output Jitter: 125ps max, 85ps typical
  • Low Power: Typically 430mW
  • No External Serial Data Rate Setting or VCO Filtering Components Required*
  • Fast PLL Lock Time: < 150µs Typical at 1.485 Gbps
  • Adjustable Depth Video FIFO for Timing Alignment
  • Built-in Self-Test (BIST) and Video Test Pattern Generator (TPG)* * Patent applications made or pending.
  • Automatic EDH/CRC Word and Flag Generation and Insertion
  • On-Chip Ancillary Data FIFO and Insertion Control Circuitry
  • Flexible Control and Configuration I/O Port
  • LVCMOS Compatible Data and Control Inputs and Outputs
  • 75Ω ECL-Compatible, Differential, Serial Cable-Driver Outputs
  • 3.3V I/O Power Supply and 2.5V Logic Power Supply Operation
  • 64-pin TQFP Package

All trademarks are the property of their respective owners.

  • SDTV/HDTV Serial Digital Video Standard Compliant
  • Supports 270 Mbps, 360 Mbps, 540 Mbps, 1.4835Gbps and 1.485 Gbps SDV Data Rates with Auto-Detection
  • Low Output Jitter: 125ps max, 85ps typical
  • Low Power: Typically 430mW
  • No External Serial Data Rate Setting or VCO Filtering Components Required*
  • Fast PLL Lock Time: < 150µs Typical at 1.485 Gbps
  • Adjustable Depth Video FIFO for Timing Alignment
  • Built-in Self-Test (BIST) and Video Test Pattern Generator (TPG)* * Patent applications made or pending.
  • Automatic EDH/CRC Word and Flag Generation and Insertion
  • On-Chip Ancillary Data FIFO and Insertion Control Circuitry
  • Flexible Control and Configuration I/O Port
  • LVCMOS Compatible Data and Control Inputs and Outputs
  • 75Ω ECL-Compatible, Differential, Serial Cable-Driver Outputs
  • 3.3V I/O Power Supply and 2.5V Logic Power Supply Operation
  • 64-pin TQFP Package

All trademarks are the property of their respective owners.

The LMH0030 SMPTE 292M/259M Digital Video Serializer with Ancillary Data FIFO and Integrated Cable Driver is a monolithic integrated circuit that encodes, serializes and transmits bit-parallel digital video data conforming to SMPTE 125M and 267M standard definition, 10-bit wide component video and SMPTE 260M, 274M, 295M and 296M high-definition, 20-bit wide component video standards. The LMH0030 operates at SMPTE 259M serial data rates of 270 Mbps, 360 Mbps, the SMPTE 344M serial data rate of 540 Mbps, and the SMPTE 292M serial data rates of 1483.5 and 1.485 Gbps. The serial data clock frequency is internally generated and requires no external frequency setting, trimming or filtering components.

The LMH0030 performs functions which include: parallel-to-serial data conversion, SMPTE standard data encoding, NRZ to NRZI data format conversion, serial data clock generation and encoding with the serial data, automatic video rate and format detection, ancillary data packet management and insertion, and serial data output driving. The LMH0030 has circuitry for automatic EDH/CRC character and flag generation and insertion per SMPTE RP-165 (standard definition) or SMPTE 292M (high definition). Optional LSB dithering is implemented which prevents pathological pattern generation. Unique to the LMH0030 are its video and ancillary data FIFOs. The video FIFO allows the video data to be delayed from 0 to 4 parallel data clock periods for video timing purposes. The ancillary data port and on-chip FIFO and control circuitry store and insert ancillary flags, data packets and checksums into the ancillary data space. The LMH0030 also has an exclusive built-in self-test (BIST) and video test pattern generator (TPG) with SD and HD component video test patterns: reference black, PLL and EQ pathologicals and color bars in 4:3 and 16:9 raster formats for NTSC and PAL standards*. The color bar patterns feature optional bandwidth limiting coding in the chroma and luma transitions.

The LMH0030 has a unique multi-function I/O port for immediate access to control and configuration settings. This port may be programmed to provide external access to control functions and indicators as inputs and outputs. The designer can thus customize the LMH0030 to fit the desired application. At power-up or after a reset command, the LMH0030 is auto-configured to a default operating condition. Separate power pins for the output driver, PLL and the serializer improve power supply rejection, output jitter and noise performance.

The LMH0030's internal circuitry is powered from +2.5V and the I/O circuitry from a +3.3V supply. Power dissipation is typically 430mW at 1.485 Gbps including two 75Ω AC-coupled and back-matched output loads. The device is packaged in a 64-pin TQFP.

The LMH0030 SMPTE 292M/259M Digital Video Serializer with Ancillary Data FIFO and Integrated Cable Driver is a monolithic integrated circuit that encodes, serializes and transmits bit-parallel digital video data conforming to SMPTE 125M and 267M standard definition, 10-bit wide component video and SMPTE 260M, 274M, 295M and 296M high-definition, 20-bit wide component video standards. The LMH0030 operates at SMPTE 259M serial data rates of 270 Mbps, 360 Mbps, the SMPTE 344M serial data rate of 540 Mbps, and the SMPTE 292M serial data rates of 1483.5 and 1.485 Gbps. The serial data clock frequency is internally generated and requires no external frequency setting, trimming or filtering components.

The LMH0030 performs functions which include: parallel-to-serial data conversion, SMPTE standard data encoding, NRZ to NRZI data format conversion, serial data clock generation and encoding with the serial data, automatic video rate and format detection, ancillary data packet management and insertion, and serial data output driving. The LMH0030 has circuitry for automatic EDH/CRC character and flag generation and insertion per SMPTE RP-165 (standard definition) or SMPTE 292M (high definition). Optional LSB dithering is implemented which prevents pathological pattern generation. Unique to the LMH0030 are its video and ancillary data FIFOs. The video FIFO allows the video data to be delayed from 0 to 4 parallel data clock periods for video timing purposes. The ancillary data port and on-chip FIFO and control circuitry store and insert ancillary flags, data packets and checksums into the ancillary data space. The LMH0030 also has an exclusive built-in self-test (BIST) and video test pattern generator (TPG) with SD and HD component video test patterns: reference black, PLL and EQ pathologicals and color bars in 4:3 and 16:9 raster formats for NTSC and PAL standards*. The color bar patterns feature optional bandwidth limiting coding in the chroma and luma transitions.

The LMH0030 has a unique multi-function I/O port for immediate access to control and configuration settings. This port may be programmed to provide external access to control functions and indicators as inputs and outputs. The designer can thus customize the LMH0030 to fit the desired application. At power-up or after a reset command, the LMH0030 is auto-configured to a default operating condition. Separate power pins for the output driver, PLL and the serializer improve power supply rejection, output jitter and noise performance.

The LMH0030's internal circuitry is powered from +2.5V and the I/O circuitry from a +3.3V supply. Power dissipation is typically 430mW at 1.485 Gbps including two 75Ω AC-coupled and back-matched output loads. The device is packaged in a 64-pin TQFP.

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기술 자료

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11개 모두 보기
유형 직함 날짜
* Data sheet LMH0030 292M/259M Dig Video Serial w/Vid & Ancill Data FIFO & Integ Cable Drvr datasheet (Rev. G) 2013/04/15
Selection guide Broadcast and Professional Video Interface Solutions (Rev. E) 2017/04/05
Application note AN-1334 The LMH0030 in Segmented Frames Applications (Rev. B) 2013/04/26
Application note AN-1336 LMH0030 or LMH0031 Control Port Bussed Operation (Rev. B) 2013/04/26
Application note AN-1943 Understanding Serial Digital Video Bit Rates (Rev. A) 2013/04/26
Application note AN-2145 Power Considerations for SDI Products (Rev. B) 2013/04/26
Application note AN-2146 Power Design for SDI and Other Noise-Sensitive Devices (Rev. A) 2013/04/26
Application note Enhancing LMH0031 Jitter Perf w/Easy-To-Use VCXOs (Rev. B) 2013/04/26
Application note High-Speed Board Layout Challenges in FPGA/SDI Sub-Systems 2009/11/12
Application note LMH0030 (CLC030), LMH0031 (CLC031A) ‚Çô Frequently Asked Questions (FAQs) 2008/08/26
Application note Timing is Everything ‚Çô The Broadcast Video Signal Path 2007/08/02

설계 및 개발

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사용 설명서: PDF
패키지 CAD 기호, 풋프린트 및 3D 모델
TQFP (PAG) 64 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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