SM320DM355-EP
- High-Performance Digital Media System-on-Chip
- 135-, 216-, and 270-MHz ARM926EJ-S Clock
Rate; and Up to 216 MHz in M-Temp (M216EP) - Fully Software-Compatible With ARM9™
- 135-, 216-, and 270-MHz ARM926EJ-S Clock
- ARM926EJ-S Core
- Support for 32-Bit and 16-Bit (Thumb Mode)
Instruction Sets - DSP Instruction Extensions and Single Cycle MAC
- ARM® Jazelle® Technology
- EmbeddedICE-RT™ Logic for Real-Time Debug
- Support for 32-Bit and 16-Bit (Thumb Mode)
- ARM9 Memory Architecture
- 16K-Byte Instruction Cache
- 8K-Byte Data Cache
- 32K-Byte RAM
- 8K-Byte ROM
- Little Endian
- MPEG4/JPEG Coprocessor
- Fixed Function Coprocessor Supports:
- MPEG4 SP Codec at HD (720p), D1, VGA, SIF
- JPEG Codec up to 50M Pixels per Second
- Fixed Function Coprocessor Supports:
- Video Processing Subsystem
- Front End Provides:
- Hardware IPIPE for Real-Time Image Processing
- Up to 14-bit CCD/CMOS Digital Interface
- 16-/8-bit Generic YcBcR-4:2 Interface (BT.601)
- 10-/8-bit CCIR6565/BT655 Interface
- Up to 75-MHz Pixel Clock
- Histogram Module
- Resize Engine
- Resize Images From 1/16x to 8x
- Separate Horizontal/Vertical Control
- Two Simultaneous Output Paths
- Back End Provides:
- Hardware On-Screen Display (OSD)
- Composite NTSC/PAL video encoder output
- 8-/16-bit YCC and Up to 18-Bit RGB666
Digital Output - BT.601/BT.656 Digital YCbCr 4:2:2
(8-/16-Bit) Interface - Supports digital HDTV (720p/1080i) output for
connection to external encoder
- Front End Provides:
- External Memory Interfaces (EMIFs)
- DDR2 and mDDR SDRAM 16-bit wide EMIF
With 256 MByte Address Space (1.8-V I/O) - Asynchronous16-/8-bit Wide EMIF (AEMIF)
- Flash Memory Interfaces
- NAND (8-/16-bit Wide Data)
- OneNAND(16-bit Wide Data)
- Flash Memory Interfaces
- DDR2 and mDDR SDRAM 16-bit wide EMIF
- Flash Card Interfaces
- Two Multimedia Card (MMC) / Secure
Digital (SD/SDIO) - SmartMedia
- Two Multimedia Card (MMC) / Secure
- Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels) - USB Port with Integrated 2.0 High-Speed PHY
that Supports- USB 2.0 Full and High-Speed Device
- USB 2.0 Low, Full, and High-Speed Host
- Three 64-Bit General-Purpose Timers (each
configurable as two 32-bit timers) - One 64-Bit Watch Dog Timer
- Three UARTs (One fast UART with RTS and
CTS Flow Control) - Three Serial Port Interfaces (SPI) each with
two Chip-Selects - One Master/Slave Inter-Integrated Circuit (I2C) Bus®
- Two Audio Serial Port (ASP)
- I2S and TDM I2S
- AC97 Audio Codec Interface
- S/PDIF via Software
- Standard Voice Codec Interface (AIC12)
- SPI Protocol (Master Mode Only)
- Four Pulse Width Modulator (PWM) Outputs
- Four RTO (Real Time Out) Outputs
- Up to 104 General-Purpose I/O (GPIO) Pins
(Multiplexed with Other Device Functions) - On-Chip ARM ROM Bootloader (RBL) to Boot
From NAND Flash, MMC/SD, USB, or UART - Configurable Power-Saving Modes
- Crystal or External Clock Input (typically
24 MHz or 36 MHz) - Flexible PLL Clock Generators
- Debug Interface Support
- IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
- ETB™ (Embedded Trace Buffer™) with
4K-Bytes Trace Buffer memory - Device Revision ID Readable by ARM
- 337-Pin Ball Grid Array (BGA) Package
(GCE Suffix), 0.65-mm Ball Pitch - 90nm Process Technology
- 3.3-V and 1.8-V I/O, 1.3-V Internal
- SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS
- Controlled Baseline
- One Assembly/Test Site
- One Fabrication Site
- Available in Military (–55°C/125°C)
Temperature Range(1) - Extended Product Life Cycle
- Extended Product-Change Notification
- Product Traceability
(1) Additional temperature ranges are available - contact factory
Windows is a trademark of Microsoft.
All other trademarks are the property of their respective owners.
The DM355 is a highly integrated, programmable platform for digital still camera, digital photo frames, IP security cameras, 4-channel digital video recorders, video door bell application, and other low cost portable digital video applications. Designed to offer portable video designers and manufacturers the ability to produce affordable portable digital video solutions with high picture quality, the DM355 combines high performance MPEG4 HD (720p) codecs and JPEG codecs up to 50M pixels per second, high quality, and low power consumption at a very low price point. The DM355 also enables seamless interface to most additional external devices required for a complete digital camera implementation. The interface is flexible enough to support various types of CCD and CMOS sensors, signal conditioning circuits, power management, DDR/mDDR memory, SRAM, NAND, shutter, Iris and auto-focus motor controls, etc.
The DM355 processor core is an ARM926EJ-S RISC processor. The ARM926EJ-S is a 32-bit processor core that performs 32-bit and 16-bit instructions and processes 32-bit, 16-bit, and
8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core incorporates:
- A coprocessor 15 (CP15) and protection module
- Data and program Memory Management Units (MMUs) with table look-aside buffers.
- Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).
DM355 performance is enhanced by its MPEG4/JPEG coprocessor. The MPEG4/JPEG coprocessor performs the computational operations required for image processing; JPEG compression and MPEG4 video and imaging standard. The MPEG4/JPEG coprocessor supports MPEG4 SP at HD (720p), D1, VGA, SIF encode/decode resolutions and JPEG encode/decode up to 50M pixels per second.
The DM355 device has a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals:
- A Video Processing Front-End (VPFE)
- A Video Processing Back-End (VPBE)
The VPFE port provides an interface for CCD/CMOS imager modules and video decoders. The VPBE provides hardware On Screen Display (OSD) support and composite NTSC/PAL and digital LCD output.
The DM355 peripheral set includes:
- An inter-integrated circuit (I2C) Bus interface
- Two audio serial ports (ASP)
- Three 64-bit general-purpose timers each configurable as two independent 32-bit timers
- A 64-bit watchdog timer
- Up to 104-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals
- Three UARTs with hardware handshaking support on one UART
- Three serial port Interfaces (SPI)
- Four pulse width modulator (PWM) peripherals
- Four real time out (RTO) outputs
- Two Multi-Media Card / Secure Digital (MMC/SD/SDIO) interfaces
- Wireless interfaces (Bluetooth, WLAN, WUSB) through SDIO
- A USB 2.0 full and high-speed device and host interface
- Two external memory interfaces:
- An asynchronous external memory interface (AEMIF) for slower memories/peripherals such as NAND and OneNAND,
- A high speed synchronous memory interface for DDR2/mDDR.
For software development support the DM355 has a complete set of ARM development tools which ninclude: C compilers, assembly optimizers to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | Digital Media System-on-Chip (DMSoC) datasheet | 2009/07/31 | |
| * | VID | SM320DM355-EP VID V6209643 | 2016/06/21 | |
| * | Radiation & reliability report | SM32DM355GCEM216EP Reliability Report | 2011/08/26 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
TMDSEMU200-U — XDS200 USB 디버그 프로브
XDS200은 TI 임베디드 디바이스 디버깅에 사용되는 디버그 프로브(에뮬레이터)입니다. XDS200은 저렴한 XDS110 및 고성능 XDS560v2에 비해 저렴한 비용으로 우수한 성능을 균형 있게 제공합니다. 단일 포드에서 광범위한 표준(IEEE1149.1, IEEE1149.7, SWD)을 지원합니다. 모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 Arm® 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 코어 추적의 경우 XDS560v2 PRO TRACE가 (...)
TMDSEMU560V2STM-U — XDS560v2 시스템 추적 USB 디버그 프로브
XDS560v2는 디버그 프로브의 XDS560™ 제품군 중 최고의 성능을 가진 제품으로, 기존의 JTAG 표준(IEEE1149.1)과 cJTAG(IEEE1149.7)를 모두 지원합니다. SWD(직렬 와이어 디버그)는 지원하지 않습니다.
모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 ARM 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 추적의 경우 XDS560v2 PRO TRACE가 필요합니다.
XDS560v2는 MIPI HSPT 60핀 커넥터(TI 14핀, (...)
TMDSEMU560V2STM-UE — XDS560v2 시스템 추적 USB 및 이더넷 디버그 프로브
The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).
All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| NFBGA (GCE) | 337 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치