홈 스위치 및 멀티플렉서 디지탈 디멀티플렉서 및 디코더
홈
스위치 및 멀티플렉서
디지탈 디멀티플렉서 및 디코더

SN54HC138

활성

3라인-8라인 디코더/디멀티플렉서

지금 주문
데이터 시트

SN54HC138

활성
데이터 시트 지금 주문

제품 상세 정보

Technology family HC Number of channels 1 Operating temperature range (°C) -55 to 125 Rating Military Supply current (max) (µA) 160
Technology family HC Number of channels 1 Operating temperature range (°C) -55 to 125 Rating Military Supply current (max) (µA) 160
CDIP (J) 16 135.3552 mm² 19.56 x 6.92 CFP (W) 16 69.319 mm² 10.3 x 6.73 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
  • Wide Operating Voltage Range (2 V to 6 V)
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 80-µA Maximum ICC
  • Typical tpd = 15 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1-µA Maximum
  • Active Low Outputs ( Selected Output is Low)
  • Incorporate Three Enable Inputs to Simplify Cascading or Data Reception
  • Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
  • Wide Operating Voltage Range (2 V to 6 V)
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 80-µA Maximum ICC
  • Typical tpd = 15 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1-µA Maximum
  • Active Low Outputs ( Selected Output is Low)
  • Incorporate Three Enable Inputs to Simplify Cascading or Data Reception

The SNx4HC138 devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The SNx4HC138 devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
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기술 자료

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15개 모두 보기
유형 직함 날짜
* Data sheet SNx4HC138 3-Line To 8-Line Decoders/Demultiplexers datasheet (Rev. G) PDF | HTML 2021/10/08
* SMD SN54HC138 SMD 84062012A 2016/06/21
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
User guide Signal Switch Data Book (Rev. A) 2003/11/14
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997/06/01
Application note Designing With Logic (Rev. C) 1997/06/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 1996/05/01
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996/04/01

설계 및 개발

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패키지 핀 CAD 기호, 풋프린트 및 3D 모델
CDIP (J) 16 Ultra Librarian
CFP (W) 16 Ultra Librarian
LCCC (FK) 20 Ultra Librarian
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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포럼 주제 모두 보기(영문)

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