인터페이스 LVDS, M-LVDS 및 PECL

SN65LVDS389

활성

8진 LVDS 드라이버

제품 상세 정보

Function Driver Protocols LVDS Number of transmitters 8 Number of receivers 0 Supply voltage (V) 3.3 Signaling rate (Mbps) 630 Input signal LVTTL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Driver Protocols LVDS Number of transmitters 8 Number of receivers 0 Supply voltage (V) 3.3 Signaling rate (Mbps) 630 Input signal LVTTL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DBT) 38 62.08 mm² 9.7 x 6.4
  • Four (’391), Eight (’389), or Sixteen (’387) Line
    Drivers Meet or Exceed the Requirements of ANSI
    EIA/TIA-644 Standard
  • Designed for Signaling Rates Up to 630 Mbps
    With Very Low Radiation (EMI)
  • Low-Voltage Differential Signaling With Typical
    Output Voltage of 350 mV and a 100-Ω Load
  • Propagation Delay Times Less Than 2.9 ns
  • Output Skew Is Less Than 150 ps
  • Part-to-Part Skew Is Less Than 1.5 ns
  • 35-mW Total Power Dissipation in Each Driver
    Operating at 200 MHz
  • Driver Is High-Impedance When Disabled or With
    VCC < 1.5 V
  • SN65’ Version Bus-Pin ESD Protection Exceeds
    15 kV
  • Packaged in Thin Shrink Small-Outline Package
    With 20-mil Pin Pitch
  • Low-Voltage TTL (LVTTL) Logic Inputs Are 5-V
    Tolerant
  • Four (’391), Eight (’389), or Sixteen (’387) Line
    Drivers Meet or Exceed the Requirements of ANSI
    EIA/TIA-644 Standard
  • Designed for Signaling Rates Up to 630 Mbps
    With Very Low Radiation (EMI)
  • Low-Voltage Differential Signaling With Typical
    Output Voltage of 350 mV and a 100-Ω Load
  • Propagation Delay Times Less Than 2.9 ns
  • Output Skew Is Less Than 150 ps
  • Part-to-Part Skew Is Less Than 1.5 ns
  • 35-mW Total Power Dissipation in Each Driver
    Operating at 200 MHz
  • Driver Is High-Impedance When Disabled or With
    VCC < 1.5 V
  • SN65’ Version Bus-Pin ESD Protection Exceeds
    15 kV
  • Packaged in Thin Shrink Small-Outline Package
    With 20-mil Pin Pitch
  • Low-Voltage TTL (LVTTL) Logic Inputs Are 5-V
    Tolerant

This family of 4, 8, and 16 differential line drivers implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the 16 current-mode drivers will deliver a minimum differential output voltage magnitude of 247 mV into a 100-Ω load when enabled.

When disabled, the driver outputs are high-impedance. Each driver input (A) and enable (EN) have an internal pulldown that will drive the input to a low level when open-circuited.

The SN65LVDS387, SN65LVDS389, and SN65LVDS391 devices are characterized for operation from –40°C to 85°C. The SN75LVDS387, SN75LVDS389, and SN75LVDS391 devices are characterized for operation from 0°C to 70°C.

This family of 4, 8, and 16 differential line drivers implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the 16 current-mode drivers will deliver a minimum differential output voltage magnitude of 247 mV into a 100-Ω load when enabled.

When disabled, the driver outputs are high-impedance. Each driver input (A) and enable (EN) have an internal pulldown that will drive the input to a low level when open-circuited.

The SN65LVDS387, SN65LVDS389, and SN65LVDS391 devices are characterized for operation from –40°C to 85°C. The SN75LVDS387, SN75LVDS389, and SN75LVDS391 devices are characterized for operation from 0°C to 70°C.

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기술 자료

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7개 모두 보기
유형 직함 날짜
* Data sheet SNx5LVDS3xx High-Speed Differential Line Drivers datasheet (Rev. G) PDF | HTML 2016/01/14
Application brief How to Support 1.8-V Signals Using a 3.3-V LVDS Driver/Receiver + Level-Shifter 2018/12/28
Application brief LVDS to Improve EMC in Motor Drives 2018/09/27
Application brief How Far, How Fast Can You Operate LVDS Drivers and Receivers? 2018/08/03
Application brief How to Terminate LVDS Connections with DC and AC Coupling 2018/05/16
Technical article Applications of Low Voltage Differential Signaling (LVDS) in Multifunction and Ind PDF | HTML 2017/08/24
Application note An Overview of LVDS Technology 1998/10/05

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

SN65LVDS387EVM — 16채널 LVDS 드라이버 평가 모듈

We have designed easy-to-use evaluation modules (EVM) for our 16-channel low-voltage differential signaling (LVDS) driver and receivers. Flexibility has been designed into these EVMs so they can be set up in a point-to-point topology (1 driver to 1 receiver) or a multidrop topology (1 driver (...)

사용 설명서: PDF
TI.com에서 구매 불가
시뮬레이션 모델

SN65/75LVDS389 IBIS Model (Rev. A)

SLLC096A.ZIP (5 KB) - IBIS Model
시뮬레이션 툴

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
시뮬레이션 툴

TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
사용 설명서: PDF
패키지 CAD 기호, 풋프린트 및 3D 모델
TSSOP (DBT) 38 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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