홈 로직 및 전압 변환 구성 가능 및 프로그래머블 로직 IC 멀티바이브레이터 원샷
홈
로직 및 전압 변환
구성 가능 및 프로그래머블 로직 IC
멀티바이브레이터 원샷

SN74AHC123A-EP

활성

EP(Enhanced Product) 듀얼 재트리거 가능 단안정 멀티바이브레이터

지금 주문
데이터 시트

SN74AHC123A-EP

활성
데이터 시트 지금 주문

제품 상세 정보

Number of channels 2 Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Technology family AHC Input type Schmitt-Trigger Output type Push-Pull Supply current (µA) 40 IOL (max) (mA) 8 IOH (max) (mA) -8 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Retriggerable Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product
Number of channels 2 Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Technology family AHC Input type Schmitt-Trigger Output type Push-Pull Supply current (µA) 40 IOL (max) (mA) 8 IOH (max) (mA) -8 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Retriggerable Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product
SOIC (D) 16 59.4 mm² 9.9 x 6
  • Controlled Baseline
    • One Assembly Site
    • One Test Site
    • One Fabrication Site
  • Extended Temperature Performance of -55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Operating Range 2-V to 5.5-V VCC
  • Schmitt-Trigger Circuitry On A, B, and CLR Inputs for Slow Input Transition Rates
  • Edge Triggered From Active-High or Active-Low Gated Logic Inputs
  • Retriggerable for Long Output Pulses
  • Overriding Clear Terminates Output Pulse
  • Glitch-Free Power-Up Reset On Outputs
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
  • Controlled Baseline
    • One Assembly Site
    • One Test Site
    • One Fabrication Site
  • Extended Temperature Performance of -55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • Operating Range 2-V to 5.5-V VCC
  • Schmitt-Trigger Circuitry On A, B, and CLR Inputs for Slow Input Transition Rates
  • Edge Triggered From Active-High or Active-Low Gated Logic Inputs
  • Retriggerable for Long Output Pulses
  • Overriding Clear Terminates Output Pulse
  • Glitch-Free Power-Up Reset On Outputs
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

The SN74AHC123A device is a dual retriggerable monostable multivibrator designed for 2-V to 5.5-V VCC operation.

This edge-triggered multivibrator features output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.

The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration can be reduced by taking CLR low.

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.

Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or high-level-active (B) input. Pulse duration can be reduced by taking CLR low. CLR can be used to override A or B inputs. The input/output timing diagram illustrates pulse control by retriggering the inputs and early clearing.

The variance in output pulse duration from device to device is less than ±0.5% (typ) for given external timing components.

During power up, Q outputs are in the low state and Q outputs are in the high state. The outputs are glitch free, without applying a reset pulse.

For additional application information on multivibrators, see the application report Designing With the SN74AHC123A and SN74AHCT123A, literature number SCLA014.

The SN74AHC123A device is a dual retriggerable monostable multivibrator designed for 2-V to 5.5-V VCC operation.

This edge-triggered multivibrator features output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.

The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration can be reduced by taking CLR low.

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.

Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or high-level-active (B) input. Pulse duration can be reduced by taking CLR low. CLR can be used to override A or B inputs. The input/output timing diagram illustrates pulse control by retriggering the inputs and early clearing.

The variance in output pulse duration from device to device is less than ±0.5% (typ) for given external timing components.

During power up, Q outputs are in the low state and Q outputs are in the high state. The outputs are glitch free, without applying a reset pulse.

For additional application information on multivibrators, see the application report Designing With the SN74AHC123A and SN74AHCT123A, literature number SCLA014.
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기술 자료

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23개 모두 보기
유형 직함 날짜
* Data sheet SN74AHC123A-EP datasheet (Rev. A) 2007/03/14
* VID SN74AHC123A-EP VID V6206665 2016/06/21
* Radiation & reliability report SN74AHC123AMDREP Reliability Report 2012/05/07
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Application note Designing With the SN74LVC1G123 Monostable Multivibrator (Rev. A) PDF | HTML 2020/03/13
Selection guide Little Logic Guide 2018 (Rev. G) 2018/07/06
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note How to Select Little Logic (Rev. A) 2016/07/26
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Product overview Design Summary for WCSP Little Logic (Rev. B) 2004/11/04
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22
Application note Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) 2002/12/02
Application note Texas Instruments Little Logic Application Report 2002/11/01
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
Design guide AHC/AHCT Designer's Guide February 2000 (Rev. D) 2000/02/24
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 1999/09/08
Product overview Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) 1998/04/01
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997/12/01
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997/08/01
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997/06/01
Application note Live Insertion 1996/10/01

설계 및 개발

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SOIC (D) 16 Ultra Librarian
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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