SN74AHC1G00

Name: SN74AHC1G00
Brand: TI
SKU: SN74AHC1G00
Price: 0.022 USD

활성

단일 2입력, 2V~5.5V NAND 게이트

지금 주문

데이터 시트

document-pdfAcrobat SN74AHC1G00 Single 2-Input Positive-NAND Gate datasheet (Rev. Q) (영어) PDF | HTML

SN74AHC1G00

활성

데이터 시트

지금 주문

제품 상세 정보

Technology family

AHC

Supply voltage (min) (V)

Supply voltage (max) (V)

5.5

Number of channels

Inputs per channel

IOL (max) (mA)

IOH (max) (mA)

-8

Input type

Standard CMOS

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Data rate (max) (Mbps)

110

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Technology family

AHC

Supply voltage (min) (V)

Supply voltage (max) (V)

5.5

Number of channels

Inputs per channel

IOL (max) (mA)

IOH (max) (mA)

-8

Input type

Standard CMOS

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Data rate (max) (Mbps)

110

Rating

Catalog

Operating temperature range (°C)

-40 to 125

SOT-23 (DBV)

8.12 mm² 2.9 x 2.8

SOT-5X3 (DRL)

2.56 mm² 1.6 x 1.6

SOT-SC70 (DCK)

4.2 mm² 2 x 2.1

Operating range: 2 V to 5.5 V
Maximum tpd of 6.5 ns at 5 V
Low power consumption: maximum ICC of 10 µA
±8-mA output drive at 5 V
Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall time
Latch-up performance exceeds 250 mA per JESD 17

Operating range: 2 V to 5.5 V
Maximum tpd of 6.5 ns at 5 V
Low power consumption: maximum ICC of 10 µA
±8-mA output drive at 5 V
Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall time
Latch-up performance exceeds 250 mA per JESD 17

The SN74AHC1G00 performs the Boolean function Y = A • B or Y = A + B in positive logic.

filter

기타 NAND 게이트 찾기

다운로드 스크립트와 함께 비디오 보기 동영상

관심 가지실만한 유사 제품

open-in-new

대안 비교

비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀

SN74HCS30

활성

슈미츠 트리거 입력을 지원하는 8입력 NAND 게이트 Larger voltage range (2V to 6V)

기술 자료

star

=TI에서 선정한 이 제품의 인기 문서

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20개 모두 보기

	유형	직함		날짜
*	Data sheet	SN74AHC1G00 Single 2-Input Positive-NAND Gate datasheet (Rev. Q)	PDF \| HTML	2024/01/31
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)		2021/07/26
	Selection guide	Little Logic Guide 2018 (Rev. G)		2018/07/06
	Selection guide	Logic Guide (Rev. AB)		2017/06/12
	Application note	How to Select Little Logic (Rev. A)		2016/07/26
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		2015/12/02
	User guide	LOGIC Pocket Data Book (Rev. B)		2007/01/16
	Product overview	Design Summary for WCSP Little Logic (Rev. B)		2004/11/04
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		2004/07/08
	Application note	Selecting the Right Level Translation Solution (Rev. A)		2004/06/22
	Application note	Advanced High-Speed CMOS (AHC) Logic Family (Rev. C)		2002/12/02
	Application note	Texas Instruments Little Logic Application Report		2002/11/01
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		2002/08/29
	Design guide	AHC/AHCT Designer's Guide February 2000 (Rev. D)		2000/02/24
	Application note	Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)		1999/09/08
	Product overview	Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C)		1998/04/01
	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices		1997/12/01
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)		1997/08/01
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)		1997/06/01
	Application note	Live Insertion		1996/10/01