홈 로직 및 전압 변환 플립플롭, 래치 및 레지스터 D형 래치
홈
로직 및 전압 변환
플립플롭, 래치 및 레지스터
D형 래치

SN74ALVTH16373

구형

3상 출력을 지원하는 2.5V/3.3V 16비트 트랜스페어런스 D형 래치

지금 주문
데이터 시트
SN74ALVTH16373은(는) 더 이상 생산되지 않습니다.
이 제품은 더 이상 생산되지 않습니다. 새로운 설계는 대체 제품을 고려해야 합니다.
open-in-new 대안 비교
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
74ACT16373 활성 3상 출력을 지원하는 16비트 D형 트랜스페어런스 래치 Lower average drive strength (24mA)
SN74ALVCH16373 활성 3상 출력을 지원하는 16bit 투명 D형 래치 Replacement

SN74ALVTH16373

구형
데이터 시트 지금 주문

제품 상세 정보

Number of channels 16 Technology family ALVT Supply voltage (min) (V) 2.3 Supply voltage (max) (V) 3.6 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 250 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 5000 Features Bus-hold, Flow-through pinout, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 16 Technology family ALVT Supply voltage (min) (V) 2.3 Supply voltage (max) (V) 3.6 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 250 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 5000 Features Bus-hold, Flow-through pinout, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Operating temperature range (°C) -40 to 85 Rating Catalog
SSOP (DL) 48 164.358 mm² 15.88 x 10.35 TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1 TVSOP (DGV) 48 62.08 mm² 9.7 x 6.4
  • State-of-the-Art Advanced BiCMOS Technology (ABT) WidebusTM Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation
  • Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC)
  • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
  • High Drive (-24/24 mA at 2.5-V and -32/64 mA at 3.3-V VCC)
  • Power Off Disables Outputs, Permitting Live Insertion
  • High-Impedance State During Power Up and Power Down Prevents Driver Conflict
  • Uses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating
  • Auto3-State Eliminates Bus Current Loading When Output Exceeds VCC + 0.5 V
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model; and Exceeds 1000 V Using Charged-Device Model, Robotic Method
  • Flow-Through Architecture Facilitates Printed Circuit Board Layout
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package

Widebus is a trademark of Texas Instruments Incorporated.
  • State-of-the-Art Advanced BiCMOS Technology (ABT) WidebusTM Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation
  • Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC)
  • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
  • High Drive (-24/24 mA at 2.5-V and -32/64 mA at 3.3-V VCC)
  • Power Off Disables Outputs, Permitting Live Insertion
  • High-Impedance State During Power Up and Power Down Prevents Driver Conflict
  • Uses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating
  • Auto3-State Eliminates Bus Current Loading When Output Exceeds VCC + 0.5 V
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model; and Exceeds 1000 V Using Charged-Device Model, Robotic Method
  • Flow-Through Architecture Facilitates Printed Circuit Board Layout
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package

Widebus is a trademark of Texas Instruments Incorporated.

The 'ALVTH16373 devices are 16-bit transparent D-type latches with 3-state outputs designed for 2.5-V or 3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

When VCC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ALVTH16373 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH16373 is characterized for operation from -40°C to 85°C.

The 'ALVTH16373 devices are 16-bit transparent D-type latches with 3-state outputs designed for 2.5-V or 3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

When VCC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ALVTH16373 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALVTH16373 is characterized for operation from -40°C to 85°C.

filter 기타 D형 래치 찾기
다운로드

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
1개 모두 보기
유형 직함 날짜
* Data sheet 2.5-V/3.3-V 16-Bit Transparent D-Type Latches With 3-State Outputs datasheet (Rev. F) 1999/01/08

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치