SN74AUP2G14
- Available in the Texas Instruments NanoStar™ package
- Low static-power consumption (ICC = 0.9µA maximum)
- Low dynamic-power consumption (Cpd = 4.3pF typical at 3.3V)
- Low input capacitance (Ci = 1.5pF typical)
- Low noise – overshoot and undershoot <10% of VCC
- Ioff supports partial-power-down mode operation
- Wide operating VCC range of 0.8V to 3.6V
- Optimized for 3.3V operation
- 3.6V I/O tolerant to support mixed-mode signal Operation
- tpd = 4.3ns maximum at 3.3V
- Suitable for point-to-point applications
- Latch-up performance exceeds 100mA Per JESD 78, Class II
- ESD performance tested per JESD 22
- 2000V human-body model (A114-B, Class II)
- 1000V charged-device model (C101)
The AUP family is TIs premier solution to the industrys low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8V to 3.6V, resulting in increased battery life (see Figure 5-1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 5-2).
The SN74AUP2G14 contains two inverters and performs the Boolean function Y = A. The device functions as two independent inverters, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 날짜 |
|---|---|---|---|---|
| * | Data sheet | SN74AUP2G14 Low-Power Dual Schmitt-Trigger Inverter datasheet (Rev. D) | PDF | HTML | 2025/06/01 |
| Selection guide | Logic Guide (Rev. AC) | PDF | HTML | 2025/11/13 | |
| Application brief | Understanding Schmitt Triggers (Rev. B) | PDF | HTML | 2025/04/17 | |
| Selection guide | Little Logic Guide 2018 (Rev. G) | 2018/07/06 | ||
| Application note | How to Select Little Logic (Rev. A) | 2016/07/26 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004/07/08 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
5-8-LOGIC-EVM — 5핀~8핀 DCK, DCT, DCU, DRL 및 DBV 패키지용 일반 논리 평가 모듈
5-8-NL-LOGIC-EVM — 5-8핀 DPW, DQE, DRY, DSF, DTM, DTQ 및 DTT 패키지를 지원하는 일반 로직 및 변환 EVM
DTT, DRY, DPW, DTM, DQE, DQM, DSF 또는 DTQ 패키지가 있는 로직 또는 변환 디바이스를 지원하도록 설계된 일반 EVM. 보드 설계는 유연한 평가가 가능합니다.
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| DSBGA (YFP) | 6 | Ultra Librarian |
| SOT-SC70 (DCK) | 6 | Ultra Librarian |
| USON (DRY) | 6 | Ultra Librarian |
| X2SON (DSF) | 6 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치