SN74LVC1G132
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
- Available in Texas Instruments
NanoStar™ and NanoFree™ Packages - Supports 5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Max tpd of 5.3 ns at 3.3 V
- Low Power Consumption, 10-µA Maximum ICC
- ±24-mA Output Drive at 3.3 V
- Ioff Supports Partial-Power-Down Mode Operation
The SN74LVC1G132 device contains one 2-input NAND gate with Schmitt-trigger inputs designed for 1.65-V to 5.5-V VCC operation and performs the Boolean function Y = A × B or Y = A + B in positive logic.
Because of Schmitt action, this device has different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.
This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
관심 가지실만한 유사 제품
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
기술 자료
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
5-8-LOGIC-EVM — 5핀~8핀 DCK, DCT, DCU, DRL 및 DBV 패키지용 일반 논리 평가 모듈
패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
---|---|---|
SOT-23 (DBV) | 5 | Ultra Librarian |
SOT-SC70 (DCK) | 5 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치