SN74LVT8980A

활성

8비트 일반 호스트 인터페이스를 갖춘 임베디드 테스트-버스 컨트롤러 IEEE STD 1149.1(JTAG) 탭 마스터

제품 상세 정보

Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Number of channels 8 IOL (max) (mA) 32 IOH (max) (mA) -15 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Partial power down (Ioff), Positive input clamp diode, Power up 3-state, Very high speed (tpd 5-10ns) Technology family LVT Rating Military Operating temperature range (°C) -40 to 85
Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Number of channels 8 IOL (max) (mA) 32 IOH (max) (mA) -15 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Partial power down (Ioff), Positive input clamp diode, Power up 3-state, Very high speed (tpd 5-10ns) Technology family LVT Rating Military Operating temperature range (°C) -40 to 85
SOIC (DW) 24 159.65 mm² 15.5 x 10.3
  • Members of Texas Instruments Broad Family of Testability Products Supporting IEEE Std 1149.1-1990 (JTAG) Test Access Port (TAP) and Boundary-Scan Architecture
  • Provide Built-In Access to IEEE Std 1149.1 Scan-Accessible Test/Maintenance Facilities at Board and System Levels
  • While Powered at 3.3 V, the TAP Interface Is Fully 5-V Tolerant for Mastering Both 5-V and/or 3.3-V IEEE Std 1149.1 Targets
  • Simple Interface to Low-Cost 3.3-V Microprocessors/Microcontrollers Via 8-Bit Asynchronous Read/Write Data Bus
  • Easy Programming Via Scan-Level Command Set and Smart TAP Control
  • Transparently Generate Protocols to Support Multidrop TAP Configurations Using TI’s Addressable Scan Port
  • Flexible TCK Generator Provides Programmable Division, Gated-TCK, and Free-Running-TCK Modes
  • Discrete TAP Control Mode Supports Arbitrary TMS/TDI Sequences for Noncompliant Targets
  • Programmable 32-Bit Test Cycle Counter Allows Virtually Unlimited Scan/Test Length
  • Accommodate Target Retiming (Pipeline) Delays of up to 15 TCK Cycles
  • Test Output Enable (TOE)\ Allows for External Control of TAP Signals
  • High-Drive Outputs (–32-mA IOH, 64-mA IOL) at TAP Support Backplane Interface and/or High Fanout

  • Members of Texas Instruments Broad Family of Testability Products Supporting IEEE Std 1149.1-1990 (JTAG) Test Access Port (TAP) and Boundary-Scan Architecture
  • Provide Built-In Access to IEEE Std 1149.1 Scan-Accessible Test/Maintenance Facilities at Board and System Levels
  • While Powered at 3.3 V, the TAP Interface Is Fully 5-V Tolerant for Mastering Both 5-V and/or 3.3-V IEEE Std 1149.1 Targets
  • Simple Interface to Low-Cost 3.3-V Microprocessors/Microcontrollers Via 8-Bit Asynchronous Read/Write Data Bus
  • Easy Programming Via Scan-Level Command Set and Smart TAP Control
  • Transparently Generate Protocols to Support Multidrop TAP Configurations Using TI’s Addressable Scan Port
  • Flexible TCK Generator Provides Programmable Division, Gated-TCK, and Free-Running-TCK Modes
  • Discrete TAP Control Mode Supports Arbitrary TMS/TDI Sequences for Noncompliant Targets
  • Programmable 32-Bit Test Cycle Counter Allows Virtually Unlimited Scan/Test Length
  • Accommodate Target Retiming (Pipeline) Delays of up to 15 TCK Cycles
  • Test Output Enable (TOE)\ Allows for External Control of TAP Signals
  • High-Drive Outputs (–32-mA IOH, 64-mA IOL) at TAP Support Backplane Interface and/or High Fanout

The ’LVT8980A embedded test-bus controllers (eTBCs) are members of the TI broad family of testability integrated circuits. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit assemblies. Unlike most other devices of this family, the eTBCs are not boundary-scannable devices; rather, their function is to master an IEEE Std 1149.1 (JTAG) test access port (TAP) under the command of an embedded host microprocessor/microcontroller. Thus, the eTBCs enable the practical and effective use of the IEEE Std 1149.1 test-access infrastructure to support embedded/built-in test, emulation, and configuration/maintenance facilities at board and system levels.

The eTBCs master all TAP signals required to support one 4- or 5-wire IEEE Std 1149.1 serial test bus: test clock (TCK), test mode select (TMS), test data input (TDI), test data output (TDO), and test reset (TRST)\. All such signals can be connected directly to the associated target IEEE Std 1149.1 devices without need for additional logic or buffering. However, as well as being directly connected, the TMS, TDI, and TDO signals can be connected to distant target IEEE Std 1149.1 devices via a pipeline, with a retiming delay of up to 15 TCK cycles; the eTBCs automatically handle all associated serial-data justification.

Conceptually, the eTBCs operate as simple 8-bit memory- or I/O-mapped peripherals to a microprocessor/microcontroller (host). High-level commands and parallel data are passed to/from the eTBCs via their generic host interface, which includes an 8-bit data bus (D7–D0) and a 3-bit address bus (A2–A0). Read/write select (R/W\) and strobe (STRB)\ signals are implemented so that the critical host-interface timing is independent of the CLKIN period. An asynchronous ready (RDY) indicator is provided to hold off, or insert wait states into, a host read/write cycle when the eTBCs cannot respond immediately to the requested read/write operation.

High-level commands are issued by the host to cause the eTBCs to generate the TMS sequences necessary to move the test bus from any stable TAP-controller state to any other such stable state, to scan instruction or data through test registers in target devices, and/or to execute instructions in the Run-Test/Idle TAP state. A 32-bit counter can be programmed to allow a predetermined number of scan or execute cycles.

During scan operations, serial data that appears at the TDI input is transferred into a serial to 4 × 8-bit-parallel first-in/first-out (FIFO) read buffer, which can then be read by the host to obtain the return serial-data stream up to eight bits at a time. Serial data that is to be transmitted from the TDO output is written by the host, up to eight bits at a time, to a 4 × 8-bit-parallel to serial FIFO write buffer.

In addition to such simple state-movement, scan, and run-test operations, the eTBCs support several additional commands that provide for input-only scans, output-only scans, recirculate scans (in which TDI is mirrored back to TDO), and a scan mode that generates the protocols used to support multidrop TAP configurations using TI’s addressable scan port. Two loopback modes also are supported that allow the microprocessor/microcontroller host to monitor the TDO or TMS data streams output by the eTBCs.

The eTBCs’ flexible clocking architecture allows the user to choose between free-running (in which the TCK always follows CLKIN) and gated modes (in which the TCK output is held static except during state-move, run-test, or scan cycles) as well as to divide down TCK from CLKIN. A discrete mode also is available in which the TAP is driven strictly by read/write cycles under full control of the microprocessor/microcontroller host. These features ensure that virtually any IEEE Std 1149.1 target device or device chain can be serviced by the eTBCs, even where such may not fully comply to IEEE Std 1149.1

While most operations of the eTBCs are synchronous to CLKIN, a test-output enable (TOE)\ is provided for output control of the TAP outputs, and a reset (RST)\ input is provided for hardware reset of the eTBCs. The former can be used to disable the eTBCs so that an external controller can master the associated IEEE Std 1149.1 test bus.

The ’LVT8980A embedded test-bus controllers (eTBCs) are members of the TI broad family of testability integrated circuits. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit assemblies. Unlike most other devices of this family, the eTBCs are not boundary-scannable devices; rather, their function is to master an IEEE Std 1149.1 (JTAG) test access port (TAP) under the command of an embedded host microprocessor/microcontroller. Thus, the eTBCs enable the practical and effective use of the IEEE Std 1149.1 test-access infrastructure to support embedded/built-in test, emulation, and configuration/maintenance facilities at board and system levels.

The eTBCs master all TAP signals required to support one 4- or 5-wire IEEE Std 1149.1 serial test bus: test clock (TCK), test mode select (TMS), test data input (TDI), test data output (TDO), and test reset (TRST)\. All such signals can be connected directly to the associated target IEEE Std 1149.1 devices without need for additional logic or buffering. However, as well as being directly connected, the TMS, TDI, and TDO signals can be connected to distant target IEEE Std 1149.1 devices via a pipeline, with a retiming delay of up to 15 TCK cycles; the eTBCs automatically handle all associated serial-data justification.

Conceptually, the eTBCs operate as simple 8-bit memory- or I/O-mapped peripherals to a microprocessor/microcontroller (host). High-level commands and parallel data are passed to/from the eTBCs via their generic host interface, which includes an 8-bit data bus (D7–D0) and a 3-bit address bus (A2–A0). Read/write select (R/W\) and strobe (STRB)\ signals are implemented so that the critical host-interface timing is independent of the CLKIN period. An asynchronous ready (RDY) indicator is provided to hold off, or insert wait states into, a host read/write cycle when the eTBCs cannot respond immediately to the requested read/write operation.

High-level commands are issued by the host to cause the eTBCs to generate the TMS sequences necessary to move the test bus from any stable TAP-controller state to any other such stable state, to scan instruction or data through test registers in target devices, and/or to execute instructions in the Run-Test/Idle TAP state. A 32-bit counter can be programmed to allow a predetermined number of scan or execute cycles.

During scan operations, serial data that appears at the TDI input is transferred into a serial to 4 × 8-bit-parallel first-in/first-out (FIFO) read buffer, which can then be read by the host to obtain the return serial-data stream up to eight bits at a time. Serial data that is to be transmitted from the TDO output is written by the host, up to eight bits at a time, to a 4 × 8-bit-parallel to serial FIFO write buffer.

In addition to such simple state-movement, scan, and run-test operations, the eTBCs support several additional commands that provide for input-only scans, output-only scans, recirculate scans (in which TDI is mirrored back to TDO), and a scan mode that generates the protocols used to support multidrop TAP configurations using TI’s addressable scan port. Two loopback modes also are supported that allow the microprocessor/microcontroller host to monitor the TDO or TMS data streams output by the eTBCs.

The eTBCs’ flexible clocking architecture allows the user to choose between free-running (in which the TCK always follows CLKIN) and gated modes (in which the TCK output is held static except during state-move, run-test, or scan cycles) as well as to divide down TCK from CLKIN. A discrete mode also is available in which the TAP is driven strictly by read/write cycles under full control of the microprocessor/microcontroller host. These features ensure that virtually any IEEE Std 1149.1 target device or device chain can be serviced by the eTBCs, even where such may not fully comply to IEEE Std 1149.1

While most operations of the eTBCs are synchronous to CLKIN, a test-output enable (TOE)\ is provided for output control of the TAP outputs, and a reset (RST)\ input is provided for hardware reset of the eTBCs. The former can be used to disable the eTBCs so that an external controller can master the associated IEEE Std 1149.1 test bus.

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기술 자료

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18개 모두 보기
유형 직함 날짜
* Data sheet SN54LVT8980A, SN74LVT8980A datasheet (Rev. B) 2004/03/18
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021/07/26
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
EVM User's guide LASP Demo Board User's Guide 2005/11/01
Application note Programming CPLDs Via the 'LVT8986 LASP 2005/11/01
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002/05/22
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002/05/10
Selection guide Advanced Bus Interface Logic Selection Guide 2001/01/09
Application note LVT-to-LVTH Conversion 1998/12/08
Application note LVT Family Characteristics (Rev. A) 1998/03/01
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997/08/01
Application note Input and Output Characteristics of Digital Integrated Circuits 1996/10/01
Application note Live Insertion 1996/10/01
Application note Understanding Advanced Bus-Interface Products Design Guide 1996/05/01

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시뮬레이션 모델

SN74LVT8980A IBIS Model

SCBM082.ZIP (41 KB) - IBIS Model
패키지 CAD 기호, 풋프린트 및 3D 모델
SOIC (DW) 24 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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