홈 마이크로컨트롤러(MCU) 및 프로세서 DSP(디지털 신호 프로세서)
홈
마이크로컨트롤러(MCU) 및 프로세서
DSP(디지털 신호 프로세서)

TMS320DM641

활성

비디오/이미징 고정 소수점 디지털 신호 프로세서

지금 주문
데이터 시트
정오표

TMS320DM641

활성
데이터 시트 지금 주문

제품 상세 정보

DSP type 1 C64x DSP (max) (MHz) 500 CPU 32-/64-bit Operating system DSP/BIOS Ethernet MAC 10/100 Rating Catalog Operating temperature range (°C) to
DSP type 1 C64x DSP (max) (MHz) 500 CPU 32-/64-bit Operating system DSP/BIOS Ethernet MAC 10/100 Rating Catalog Operating temperature range (°C) to
OMFCBGA (ZNZ) 548 729 mm² 27 x 27
  • High-Performance Digital Media Processor (TMS320DM641/TMS320DM640)
    • 2.5-, 2-, 1.67-ns Instruction Cycle Time
    • 400-, 500-, 600-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 3200, 4000, 4800 MIPS
    • Fully Software-Compatible With C64x™
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2™ Increased Orthogonality
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • Endianess: Little Endian, Big Endian
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 1024M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
    • 8 Independent Transmit (TX) and 1 Receive (RX) Channel
  • Management Data Input/Output (MDIO)
  • Two Configurable Video Ports (DM641)
  • One Configurable Video Port (DM640)
    • Providing a Glueless I/F to Common Video Decoder and Encoder Devices
    • Supports Multiple Resolutions and Video Standards
  • VCXO Interpolated Control Port (VIC)
    • Supports Audio/Video Synchronization
  • Host-Port Interface (HPI) [16-Bit] (DM641)
  • Multichannel Audio Serial Port (McASP)
    • Four Serial Data Pins
    • Wide Variety of I2S and Similar Bit Stream Format
    • Integrated Digital Audio I/F Transmitter Supports S/PDIF, IEC60958-1, AES-3, CP-430 Formats
  • Inter-Integrated Circuit (I2C) Bus
  • Two Multichannel Buffered Serial Ports
  • Three 32-Bit General-Purpose Timers
  • Eight General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible
  • 548-Pin Ball Grid Array (BGA) Package (GDK and ZDK Suffixes), 0.8-mm Ball Pitch
  • 548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
  • 0.13-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V I/Os, 1.2-V Internal (-400, -500)
  • 3.3-V I/Os, 1.4-V Internal (-600)

C64x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000 and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
  • High-Performance Digital Media Processor (TMS320DM641/TMS320DM640)
    • 2.5-, 2-, 1.67-ns Instruction Cycle Time
    • 400-, 500-, 600-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 3200, 4000, 4800 MIPS
    • Fully Software-Compatible With C64x™
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2™ Increased Orthogonality
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • Endianess: Little Endian, Big Endian
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 1024M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
    • 8 Independent Transmit (TX) and 1 Receive (RX) Channel
  • Management Data Input/Output (MDIO)
  • Two Configurable Video Ports (DM641)
  • One Configurable Video Port (DM640)
    • Providing a Glueless I/F to Common Video Decoder and Encoder Devices
    • Supports Multiple Resolutions and Video Standards
  • VCXO Interpolated Control Port (VIC)
    • Supports Audio/Video Synchronization
  • Host-Port Interface (HPI) [16-Bit] (DM641)
  • Multichannel Audio Serial Port (McASP)
    • Four Serial Data Pins
    • Wide Variety of I2S and Similar Bit Stream Format
    • Integrated Digital Audio I/F Transmitter Supports S/PDIF, IEC60958-1, AES-3, CP-430 Formats
  • Inter-Integrated Circuit (I2C) Bus
  • Two Multichannel Buffered Serial Ports
  • Three 32-Bit General-Purpose Timers
  • Eight General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible
  • 548-Pin Ball Grid Array (BGA) Package (GDK and ZDK Suffixes), 0.8-mm Ball Pitch
  • 548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
  • 0.13-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V I/Os, 1.2-V Internal (-400, -500)
  • 3.3-V I/Os, 1.4-V Internal (-600)

C64x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000 and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.

The TMS320C64x™ DSPs (including the TMS320DM641 and TMS320DM640 devices) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320DM641 (DM641) and TMS320DM640 (DM640) devices are based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the DM641 device offers cost-effective solutions to high-performance DSP programming challenges.

With performance of up to 3200 million instructions per second (MIPS) at a clock rate of 400 MHz, the DM640 device offers cost-effective solutions to high-performance DSP programming challenges.

The DM641/DM640 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs)-with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI™ architecture. The DM641 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The DM640 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 1600 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 3200 MMACS. The DM641/DM640 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The DM641/DM640 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 1-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: two configurable video ports (DM641); one configurable video port (DM640); a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO interpolated control port (VIC); one 4-bit multichannel buffered audio serial port (McASP0); an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a 16-bit host-port interface (HPI16); a 8-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 32-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

The DM641 device has two single-channel 8-bit configurable video port peripherals (VP0 and VP1). The DM640 device has one single-channel 8-bit configurable video port peripheral (VP0). These video port peripherals provide a glueless interface to common video decoder and encoder devices. The DM641/DM640 video port peripherals support multiple resolutions and video standards (e. g., CCIR601 and ITU-).

These video port peripherals are configurable and can support either video capture and/or video display modes.

For more details on the Video Port peripherals, see the TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).

The McASP0 port supports one transmit and one receive clock zone, with four serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The DM641/DM640 has sufficient bandwidth to support all 4 serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.

In addition, the McASP0 transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.

McASP0 also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range.

The VCXO interpolated control (VIC) port provides digital-to-analog conversion with resolution from 9-bits to up to 16-bits. The output of the VIC is a single bit interpolated D/A output. For more details on the VIC port, see the TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).

The ethernet media access controller (EMAC) provides an efficient interface between the DM641/DM640 DSP core processor and the network. The DM641/DM640 EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The DM641/DM640 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception. For more details on the EMAC, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device without continuously performing costly MDIO accesses. For more details on the MDIO, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The I2C0 port on the TMS320DM641/DM640 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The DM641/DM640 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code

The TMS320C64x™ DSPs (including the TMS320DM641 and TMS320DM640 devices) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320DM641 (DM641) and TMS320DM640 (DM640) devices are based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the DM641 device offers cost-effective solutions to high-performance DSP programming challenges.

With performance of up to 3200 million instructions per second (MIPS) at a clock rate of 400 MHz, the DM640 device offers cost-effective solutions to high-performance DSP programming challenges.

The DM641/DM640 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs)-with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI™ architecture. The DM641 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The DM640 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 1600 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 3200 MMACS. The DM641/DM640 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The DM641/DM640 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 1-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: two configurable video ports (DM641); one configurable video port (DM640); a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO interpolated control port (VIC); one 4-bit multichannel buffered audio serial port (McASP0); an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a 16-bit host-port interface (HPI16); a 8-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 32-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

The DM641 device has two single-channel 8-bit configurable video port peripherals (VP0 and VP1). The DM640 device has one single-channel 8-bit configurable video port peripheral (VP0). These video port peripherals provide a glueless interface to common video decoder and encoder devices. The DM641/DM640 video port peripherals support multiple resolutions and video standards (e. g., CCIR601 and ITU-).

These video port peripherals are configurable and can support either video capture and/or video display modes.

For more details on the Video Port peripherals, see the TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).

The McASP0 port supports one transmit and one receive clock zone, with four serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The DM641/DM640 has sufficient bandwidth to support all 4 serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.

In addition, the McASP0 transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.

McASP0 also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range.

The VCXO interpolated control (VIC) port provides digital-to-analog conversion with resolution from 9-bits to up to 16-bits. The output of the VIC is a single bit interpolated D/A output. For more details on the VIC port, see the TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).

The ethernet media access controller (EMAC) provides an efficient interface between the DM641/DM640 DSP core processor and the network. The DM641/DM640 EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The DM641/DM640 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception. For more details on the EMAC, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device without continuously performing costly MDIO accesses. For more details on the MDIO, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The I2C0 port on the TMS320DM641/DM640 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The DM641/DM640 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code
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* Data sheet TMS320DM641/TMS320DM640 Video/Imaging Fixed-Point Digital Signal Processors datasheet (Rev. F) 2010/10/12
* Errata TMS320DM641, TMS320DM640 DSPs Silicon Errata (Silicon Revisions 2.0,1.2,1.1,1.0) (Rev. G) 2005/08/31
User guide Emulation and Trace Headers Technical Reference Manual (Rev. I) 2012/08/09
Application note Introduction to TMS320C6000 DSP Optimization 2011/10/06
User guide TMS320C64x DSP Video Port/ VCXO Interpolated Control (VIC) Port Reference Guide (Rev. G) 2010/11/12
User guide TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) 2010/07/30
User guide TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q) 2009/07/02
User guide TMS320C6000 DSP Multi-channel Audio Serial Port (McASP) Reference Guide (Rev. J) 2008/11/20
Application note TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E) 2007/09/04
Application note Migrating from TMS320DM642/3/1/0 to the TMS320DM648/7 2007/06/07
Application note Thermal Considerations for the DM64xx, DM64x, and C6000 Devices 2007/05/20
User guide TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E) 2007/04/11
Product overview TMS320C6000 DSP TCP/IP Stack Software (Rev. C) 2007/04/04
User guide TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (Rev. D) 2007/03/26
User guide TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (Rev. G) 2006/12/14
User guide TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (Rev. C) 2006/11/15
User guide TMS320C64x DSP Two-Level Internal Memory Reference Guide (Rev. C) 2006/02/28
User guide TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide (Rev. C) 2006/01/01
Application note TMS320DM640/1 Hardware Designer's Resource Guide (Rev. A) 2005/10/24
Application note Migrating from TMS320C64x to TMS320C64x+ (Rev. A) 2005/10/20
Product overview TMS320DM64x Digital Media Processors - Product Bulletin (Rev. C) 2005/08/30
User guide TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C) 2005/03/01
Application note TMS320DM64x Power Consumption Summary (Rev. F) 2005/02/18
User guide TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B) 2005/01/25
Application note Use and Handling of Semiconductor Packages With ENIG Pad Finishes 2004/08/31
User guide TMS320C6000 Chip Support Library API Reference Guide (Rev. J) 2004/08/13
Application note High Resolution Video Using the DM642 DSP and the THS8200 Driver (Rev. A) 2004/05/03
Application note Interfacing an LCD Controller to a DM642 Video Port (Rev. B) 2004/05/03
Application note TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D) 2004/04/26
Application note TMS320C6000 Board Design: Considerations for Debug (Rev. C) 2004/04/21
User guide TMS320C6000 DSP EMAC/MDIO Module Reference Guide (Rev. A) 2004/03/26
User guide TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (Rev. A) 2004/03/25
Application note TMS320C6000 McBSP Initialization (Rev. C) 2004/03/08
Application note TMS320C6000 EDMA IO Scheduling and Performance 2004/03/05
More literature Video/Imaging Benchmarks (Rev. A) 2004/03/01
Product overview Video Security over IP (VSIP) Development Platform Product Bulletin 2003/11/05
User guide TMS320C6000 DSP Designing for JTAG Emulation Reference Guide 2003/07/31
Product overview TMS320DM64x Digital Media Development Tools Product Bulletin 2003/07/31
User guide TMS320C6000 DSP Cache User's Guide (Rev. A) 2003/05/05
Application note Using IBIS Models for Timing Analysis (Rev. A) 2003/04/15
Application note TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B) 2002/06/04
Application note TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C) 2002/04/17
Application note TMS320C6000 Board Design for JTAG (Rev. C) 2002/04/02
Application note TMS320C6000 EMIF to External Flash Memory (Rev. A) 2002/02/13
Application note Cache Usage in High-Performance DSP Applications with the TMS320C64x 2001/12/13
Application note Using a TMS320C6000 McBSP for Data Packing (Rev. A) 2001/10/31
Application note TMS320C6000 Enhanced DMA: Example Applications (Rev. A) 2001/10/24
Application note Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A) 2001/09/30
Application note TMS320C6000 Host Port to MC68360 Interface (Rev. A) 2001/09/30
Application note TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A) 2001/08/31
Application note TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A) 2001/08/31
Application note Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A) 2001/08/31
Application note TMS320C6000 System Clock Circuit Example (Rev. A) 2001/08/15
Application note TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A) 2001/07/23
Application note TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A) 2001/07/10
Application note TMS320C6000 McBSP: Interface to SPI ROM (Rev. C) 2001/06/30
Application note TMS320C6000 Host Port to MPC860 Interface (Rev. A) 2001/06/21
Application note TMS320C6000 McBSP: IOM-2 Interface (Rev. A) 2001/05/21
User guide TMS320C64x Technical Overview (Rev. B) 2001/01/30
Application note Circular Buffering on TMS320C6000 (Rev. A) 2000/09/12
Application note TMS320C6000 McBSP as a TDM Highway (Rev. A) 2000/09/11
Application note TMS320C6000 u-Law and a-Law Companding with Software or the McBSP 2000/02/02
Application note General Guide to Implement Logarithmic and Exponential Operations on Fixed-Point 2000/01/31
Application note TMS320C6000 C Compiler: C Implementation of Intrinsics 1999/12/07
Application note TMS320C6000 McBSP: I2S Interface 1999/09/08

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

디버그 프로브

TMDSEMU200-U — XDS200 USB 디버그 프로브

XDS200은 TI 임베디드 디바이스 디버깅에 사용되는 디버그 프로브(에뮬레이터)입니다. XDS200은 저렴한 XDS110 및 고성능 XDS560v2에 비해 저렴한 비용으로 우수한 성능을 균형 있게 제공합니다. 단일 포드에서 광범위한 표준(IEEE1149.1, IEEE1149.7, SWD)을 지원합니다. 모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 Arm® 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 코어 추적의 경우 XDS560v2 PRO TRACE가 (...)

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디버그 프로브

TMDSEMU560V2STM-U — XDS560v2 시스템 추적 USB 디버그 프로브

XDS560v2는 디버그 프로브의 XDS560™ 제품군 중 최고의 성능을 가진 제품으로, 기존의 JTAG 표준(IEEE1149.1)과 cJTAG(IEEE1149.7)를 모두 지원합니다. SWD(직렬 와이어 디버그)는 지원하지 않습니다.

모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 ARM 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 추적의 경우 XDS560v2 PRO TRACE가 필요합니다.

XDS560v2는 MIPI HSPT 60핀 커넥터(TI 14핀, (...)

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디버그 프로브

TMDSEMU560V2STM-UE — XDS560v2 시스템 추적 USB 및 이더넷 디버그 프로브

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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드라이버 또는 라이브러리

SPRC090 — Download TMS320C6000 Chip Support Library

The Chip Support Library (CSL) provides an application programming interface (API) used for configuring and controlling the DSP on-chip peripherals for ease of use, compatibility between various C6000 devices and hardware abstraction. This will shorten development time by providing standardization (...)
지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
DSP(디지털 신호 프로세서)
TMS320C6412 — C64x 고정 소수점 DSP - 최대 720MHz, McBSP, McASP, I2cC, 이더넷 TMS320C6414 — C64x 고정 소수점 DSP - 최대 720MHz, McBSP TMS320C6414T — C64x 고정 소수점 DSP - 최대 1GHz, McBSP TMS320C6415 — C64x 고정 소수점 DSP - 최대 720MHz, McBSP, PCI TMS320C6415T — C64x 고정 소수점 DSP - 최대 850MHz, McBSP, PCI TMS320C6416 — C64x 고정 소수점 DSP - 최대 720MHz, McBSP, PCI, VCP/TCP TMS320C6416T — C64x 고정 소수점 DSP - 최대 850MHz, McBSP, PCI, VCP/TCP TMS320C6701 — C67x 부동 소수점 DSP - 최대 167MHz, McBSP TMS320DM640 — 비디오/이미징 고정 소수점 디지털 신호 프로세서 TMS320DM641 — 비디오/이미징 고정 소수점 디지털 신호 프로세서 TMS320DM642 — 비디오/이미징 고정 소수점 디지털 신호 프로세서 TMS320DM642Q — 비디오/이미징 고정 소수점 디지털 신호 프로세서
다운로드
드라이버 또는 라이브러리

SPRC122 — C62x/C64x Fast Run-Time Support Library

The C62x/64x FastRTS Library is an optimized, floating-point function library for C programmers using either TMS320C62x or TMS320C64x devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By replacing the current (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
DSP(디지털 신호 프로세서)
SM320C6201-EP — 향상된 제품 C6201 고정 소수점 DSP SM320C6455-EP — EP(Enhanced Product) C6455 고정 소수점 DSP SMJ320C6201B — 고정 소수점 디지털 신호 프로세서, 군사용 SMJ320C6203 — 군사용 등급 C62x 고정 소수점 DSP - 세라믹 패키지 TMS320C6202B — C62x 고정 소수점 DSP - 최대 300MHz, 384KB TMS320C6203B — C62x 고정 소수점 DSP - 최대 300MHz, 896KB TMS320C6204 — 고정소수점 디지털 신호 프로세서 TMS320C6205 — 고정소수점 디지털 신호 프로세서 TMS320C6211B — C62x 고정 소수점 DSP - 최대 167MHz TMS320C6412 — C64x 고정 소수점 DSP - 최대 720MHz, McBSP, McASP, I2cC, 이더넷 TMS320C6414 — C64x 고정 소수점 DSP - 최대 720MHz, McBSP TMS320C6414T — C64x 고정 소수점 DSP - 최대 1GHz, McBSP TMS320C6415 — C64x 고정 소수점 DSP - 최대 720MHz, McBSP, PCI TMS320C6415T — C64x 고정 소수점 DSP - 최대 850MHz, McBSP, PCI TMS320C6416 — C64x 고정 소수점 DSP - 최대 720MHz, McBSP, PCI, VCP/TCP TMS320C6416T — C64x 고정 소수점 DSP - 최대 850MHz, McBSP, PCI, VCP/TCP TMS320C6421 — C64x+ 고정 소수점 DSP - 최대 600MHz, 8비트 EMIFA, 16비트 DDR2, SDRAM TMS320C6421Q — C64x+ 고정 소수점 DSP - 최대 600MHz, 8비트 EMIFA, 16비트 DDR2 TMS320C6424 — C64x+ 고정 소수점 DSP - 최대 600MHz, 16/8비트 EMIFA, 32/16비트 DDR2, SDRAM TMS320C6424Q — C64x+ 고정 소수점 DSP - 최대 600MHz, 16/8비트 EMIFA, 32/16비트 DDR2 TMS320C6452 — C64x+ 고정 소수점 DSP - 최대 900MHz, 1Gbps 이더넷 TMS320C6454 — C64x+ 고정 소수점 DSP - 최대 1GHz, 64비트 EMIFA, 32/16비트 DDR2, 1Gbps 이더넷 TMS320C6455 — C64x+ 고정 소수점 DSP 최대 1.2GHz, 64비트 EMIFA, 32/16비트 DDR2, 1Gbps 이더넷 TMS320C6457 — 통신 인프라 디지털 신호 프로세서 TMS320C6474 — 멀티코어 디지털 신호 프로세서 TMS320DM640 — 비디오/이미징 고정 소수점 디지털 신호 프로세서 TMS320DM641 — 비디오/이미징 고정 소수점 디지털 신호 프로세서 TMS320DM642 — 비디오/이미징 고정 소수점 디지털 신호 프로세서 TMS320DM642Q — 비디오/이미징 고정 소수점 디지털 신호 프로세서 TMS320DM6431 — 디지털 미디어 프로세서 TMS320DM6431Q — 디지털 미디어 프로세서, 최대 2400MIPS, 300MHz 클럭 속도 TMS320DM6433 — 디지털 미디어 프로세서 TMS320DM6435 — 디지털 미디어 프로세서 TMS320DM6435Q — 디지털 미디어 프로세서, 최대 4800MIPS, 600MHz 클록 속도, McASP 1개, McBSP 1개 TMS320DM6437 — 디지털 미디어 프로세서 TMS320DM6437Q — 디지털 미디어 프로세서, 최대 4800MIPS, 600MHz 클록 속도, MCASP 1개, McBSP 2개 TMS320DM6441 — DaVinci 디지털 미디어 시스템 온 칩 TMS320DM6443 — DaVinci 디지털 미디어 시스템 온 칩 TMS320DM6446 — DaVinci 디지털 미디어 시스템 온 칩
다운로드
드라이버 또는 라이브러리

TELECOMLIB — 텔레콤 및 미디어 라이브러리 - TMS320C64x+ 및 TMS320C55x 프로세서를 위한 FAXLIB, VoLIB 및 AEC/AER

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
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시뮬레이션 모델

DM641 GDK BSDL Model

SPRM134.ZIP (9 KB) - BSDL Model
다운로드
시뮬레이션 모델

DM641 GDK/GNZ IBIS Model

SPRM125.ZIP (106 KB) - IBIS Model
다운로드
시뮬레이션 모델

DM641 GNZ BSDL Model

SPRM131.ZIP (9 KB) - BSDL Model
다운로드
패키지 핀 CAD 기호, 풋프린트 및 3D 모델
OMFCBGA (ZNZ) 548 Ultra Librarian
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  • 납 마감/볼 재질
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